Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 419

PCI-to-PCI Bridge Registers (D30:F0)
Bit
11
10:9
8
7:5
4
3
2:0
11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
the RID Register.
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h–0Bh
Default Value:
Bit
23:16
15:8
7:0
Datasheet
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
backbone.
Reserved.
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6).
Reserved.
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
Reserved
See bit description
060401h
Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is
subtractive decode
Description
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value of
Attribute:
Size:
Description
RO
8 bits
RO
24 bits
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