Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 237

Functional Description
external controller sees a NACK from the PCH, then it should restart its sequence
counter, or otherwise be aware that the NACK condition needs to be factored into
the sequence number usage.
The use of sequence numbers is not required, but is provided as a means to
ensure correct PCH FW operation.
5. When the PCH updates the Block Read data structure, the external controller gets a
NACK during this period.
To ensure atomicity of the SMBus data read with respect to the data itself, when
the data buffer is being updated, the PCH will NACK the Block Read transaction.
The update is only a few micro-seconds, so very short in terms of SMBus polling
time; therefore, the next read should be successful. The external controller
should attempt 3 reads to handle this condition before moving on.
If the Block read has started (that is, the address is ACK'ed) then the entire read
will complete successfully, and the PCH will update the data only after the SMBus
read has completed.
6. System is going from S0 to S3/4/5. Note that the thermal monitoring FW is fully
operational if the system is in S0/S1, so the following only applies to S3/4/5.
When the PCH detects the OS request to go to S3/4/5, it will take the SMLink1
controller offline as part of the system preparation. The external controller will
see a period where its transactions are getting NACK'ed, and then see SLP_S3#
assert.
This period is relatively short (a couple of seconds depending on how long all the
devices take to place themselves into the D3 state), and would be far less than
the 30 second limit mentioned above.
7. TEMP_ALERT# – Since there can be an internal reset, the TEMP_ALERT# may get
asserted after the reset. The external controller must accept this assertion and
handle it.
5.21.2.9.1 Example Algorithm for Handling Transaction
One algorithm for the transaction handling could be summarized as follows. This is just
an example to illustrate the above rules. There could be other algorithms that can
achieve the same results.
1. Perform SMBus transaction.
2. If ACK, then continue
3. If NACK
a. Try again for 2 more times, in case the PCH is busy updating data.
b. If 3 successive transactions receive NACK, then
- Ramp fans, assuming some general long reset or failure
- Try every 1-10 seconds to see if SMBus transactions are now working
- If they start then return to step 1
- If they continue to fail, then stay in this step and poll, but keep the fans
Datasheet
ramped up or implement some other failure recovery mechanism.
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