Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 649

EHCI Controller Registers (D29:F0, D26:F0)
16.1.19 PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 52h
Default Value:
Bit
15:11
10
9
8:6
5
4
3
2:0
NOTES:
1. Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the PCH is used, bits 15:11 and 8:6 in this register are writable when the
WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. The value written to this register
does not affect the hardware other than changing the value returned during a read.
2. Reset: core well, but not D3-to-D0 warm reset.
Datasheet
53h
–
C9C2h
PME Support (PME_SUP) — R/W. This 5-bit field indicates the power states in which
the function may assert PME#. The PCH EHC does not support the D1 or D2 states. For
all other states, the PCH EHC is capable of generating PME#. Software should never
need to modify this field.
D2 Support (D2_SUP) — RO.
0 = D2 State is not supported
D1 Support (D1_SUP) — RO.
0 = D1 State is not supported
Auxiliary Current (AUX_CUR) — R/W. The PCH EHC reports 375 mA maximum
suspend well current required when in the D3
Device Specific Initialization (DSI)— RO. The PCH reports 0, indicating that no
device-specific initialization is required.
Reserved
PME Clock (PME_CLK) — RO. The PCH reports 0, indicating that no PCI clock is
required to generate PME#.
Version (VER) — RO. The PCH reports 010b, indicating that it complies with Revision
1.1 of the PCI Power Management Specification.
Attribute: R/W, RO
Size: 16 bits
Description
state.
COLD
649