Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 835

Serial Peripheral Interface (SPI)
21.4.3 HSFC—Hardware Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
15:10 Reserved
Flash Data Byte Count (FDBC) — R/W. This field specifies the number of bytes to
shift in or out during the data portion of the SPI cycle. The contents of this register are
0s based with 0b representing 1 byte and 11b representing 4 bytes. The number of
9:8
bytes transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
7:3 Reserved
FLASH Cycle (FCYCLE) — R/W. This field defines the Flash SPI cycle type generated
to the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 4 bytes by setting FDBC)
2:1
01 = Reserved
10 = Write (1 up to 4 bytes by setting FDBC)
11 = Block Erase
Flash Cycle Go (FGO) — R/W/S. A write to this register with a 1 in this bit initiates a
request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
0
bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
Datasheet
MBARB + 06h
0000h
Description
Attribute: R/W, R/WS
Size: 16 bits
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