Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 834

Bit
SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
5
and clears this bit so that software can determine when read data is valid and/or when
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector
size for all Flash components.
00 = 256 Byte
01 = 4 K Byte
10 = 8 K Byte
4:3
11 = 64 K Byte
If the Flash Linear Address is less than FPBA then this field reflects the value in the
LVSCC.LBES register.
If the Flash Linear Address is greater or equal to FPBA then this field reflects the value
in the UVSCC.UBES register.
Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was
made to access the BIOS region using the direct access method or an access to the
2
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
an access security violation. This bit is cleared by software writing a 1.
Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
1 in progress. This bit remains asserted until cleared by software writing a 1 or until
hardware reset occurs due to a global reset or host partition reset in an Intel
enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in
this register.
Flash Cycle Done (FDONE) — R/W/C. The PCH sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
0 reset in an Intel
is set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
834
Description
®
ME enabled system. When this bit is set and the SPI SMI# Enable bit
Serial Peripheral Interface (SPI)
®
ME
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