Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 9

9 Register and Memory Mapping............................................................................... 349
9.1 PCI Devices and Functions................................................................................ 350
9.2 PCI Configuration Map ..................................................................................... 351
9.3 I/O Map ......................................................................................................... 351
9.3.1 Fixed I/O Address Ranges ..................................................................... 351
9.3.2 Variable I/O Decode Ranges .................................................................. 354
9.4 Memory Map................................................................................................... 355
9.4.1 Boot-Block Update Scheme.................................................................... 357
10 Chipset Configuration Registers............................................................................. 359
10.1 Chipset Configuration Registers (Memory Space) ................................................. 359
10.1.1 CIR0—Chipset Initialization Register 0..................................................... 362
10.1.2 RPC—Root Port Configuration Register .................................................... 363
10.1.3 RPFN—Root Port Function Number and Hide for PCI Express* Root Ports ..... 364
10.1.4 FLRSTAT—FLR Pending Status Register ................................................... 365
10.1.5 CIR2—Chipset Initialization Register 2..................................................... 365
10.1.6 CIR3—Chipset Initialization Register 3..................................................... 366
10.1.7 TRSR—Trap Status Register ................................................................... 366
10.1.8 TRCR—Trapped Cycle Register ............................................................... 366
10.1.9 TWDR—Trapped Write Data Register....................................................... 367
10.1.10IOTRn—I/O Trap Register (0–3) ............................................................. 367
10.1.11V0CTL—Virtual Channel 0 Resource Control Register ................................. 368
10.1.12V0STS—Virtual Channel 0 Resource Status Register .................................. 368
10.1.13V1CTL—Virtual Channel 1 Resource Control Register ................................. 369
10.1.14V1STS—Virtual Channel 1 Resource Status Register .................................. 369
10.1.15CIR31—Chipset Initialization Register 31 ................................................. 369
10.1.16CIR32—Chipset Initialization Register 32 ................................................. 370
10.1.17CIR1—Chipset Initialization Register 1..................................................... 370
10.1.18REC—Root Error Command Register ....................................................... 370
10.1.19LCAP—Link Capabilities Register ............................................................. 371
10.1.20LCTL—Link Control Register ................................................................... 371
10.1.21LSTS—Link Status Register .................................................................... 372
10.1.22DMIC—DMI Control Register .................................................................. 372
10.1.23CIR30—Chipset Initialization Register 30 ................................................. 372
10.1.24CIR5—Chipset Initialization Register 5..................................................... 372
10.1.25DMC—DMI Miscellaneous Control Register ............................................... 373
10.1.26CIR6—Chipset Initialization Register 6..................................................... 373
10.1.27CIR9—Chipset Initialization Register 9..................................................... 373
10.1.28IOBP Indexed Registers......................................................................... 373
10.1.28.1DMI IOBP Indexed Registers .................................................... 374
10.1.28.2PCIe IOBP Indexed Registers.................................................... 376
10.1.29TCTL—TCO Configuration Register .......................................................... 379
10.1.30D31IP—Device 31 Interrupt Pin Register.................................................. 380
10.1.31D30IP—Device 30 Interrupt Pin Register.................................................. 381
10.1.32D29IP—Device 29 Interrupt Pin Register.................................................. 381
10.1.33D28IP—Device 28 Interrupt Pin Register.................................................. 381
10.1.34D27IP—Device 27 Interrupt Pin Register.................................................. 383
10.1.35D26IP—Device 26 Interrupt Pin Register.................................................. 383
10.1.36D25IP—Device 25 Interrupt Pin Register.................................................. 383
10.1.37D22IP—Device 22 Interrupt Pin Register.................................................. 384
10.1.38D31IR—Device 31 Interrupt Route Register ............................................. 385
10.1.39D30IR—Device 30 Interrupt Route Register ............................................. 386
10.1.40D29IR—Device 29 Interrupt Route Register ............................................. 386
10.1.41D28IR—Device 28 Interrupt Route Register ............................................. 387
10.1.42D27IR—Device 27 Interrupt Route Register ............................................. 388
10.1.43D26IR—Device 26 Interrupt Route Register ............................................. 389
10.1.44D25IR—Device 25 Interrupt Route Register ............................................. 390
10.1.45D22IR—Device 22 Interrupt Route Register ............................................. 391
10.1.46OIC—Other Interrupt Control Register ..................................................... 392
10.1.47PRSTS—Power and Reset Status............................................................. 393
10.1.48CIR7—Chipset Initialization Register 7..................................................... 393
10.1.49PM_CFG—Power Management Configuration............................................. 394
10.1.50CIR8—Chipset Initialization Register 8..................................................... 395
10.1.51DEEP_S4_POL—Deep S4 Power Policies................................................... 395
10.1.52DEEP_S5_POL—Deep S5 Power Policies................................................... 395
10.1.53CIR10—Chipset Initialization Register 10 ................................................. 395
10.1.54CIR11—Chipset Initialization Register 11 ................................................. 396
Datasheet 9