Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 548

13.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register
Offset Address: GPIOBASE +40h
Default Value:
Lockable:
Bit
31:12 Always 0. No corresponding GPIO.
GPIO_USE_SEL3[75:64]— R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1.
2.
11:0
3.
4.
5.
This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
13.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register
Offset Address: GPIOBASE +44h
Default Value:
Lockable:
Bit
31:12 Always 0. No corresponding GPIO.
GPIO_IO_SEL3[75:72]— R/W.
0 = GPIO signal is programmed as an output.
11:8
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is
7:4 Always 0. No corresponding GPIO.
GPIO_IO_SEL3[67:64]— R/W.
0 = GPIO signal is programmed as an output.
3:0 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is
This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64.
548
00000130h (Desktop)
00000030h (Mobile)
Yes
The following bit is always 1 because it is always unmultiplexed: 8
If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as
0 and writes will have no effect.
After a full reset RSMRST# all multiplexed signals in the resume and core wells
are configured as their default function. After only a PLTRST#, the GPIOs in the
core well are configured as their default function.
When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
GPIO73 is a mobile only GPIO.
00000F00
Yes
programmed as an input.
programmed as an input.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
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