Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 97

PCH Pin States
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 3 of 6)
Signal Name
10
LAN_PHY_PWR_CTRL /
GPIO12
PLTRST#
5
SLP_A#
SLP_S3#
SLP_S4#
SLP_S5#/GPIO63
SUS_STAT#/GPIO61
SUSCLK/GPIO62
DRAMPWROK
PMSYNCH
STP_PCI#/GPIO34
8
SLP_LAN#/GPIO29
SLP_LAN# (using soft-
strap)
GPIO29 (using soft-
strap)
PROCPWRGD
SMBCLK, SMBDATA
SML0ALERT# / GPIO60
SML0DATA
SML0CLK
SML1CLK/GPIO58
SML1ALERT#/PCHHOT#/
GPIO74
SML1DATA/GPIO75
7
SPKR
JTAG_TDO
GPIO24 /
PROC_MISSING
Datasheet
Power During
1
Plane Reset
Power Management
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Suspend Low
Core Low
Core High-Z (Input)
Low
Suspend
High-Z
Processor Interface
Processor Low
SMBus Interface
Suspend High-Z
System Management Interface
Suspend High-Z
Suspend High-Z
Suspend High-Z
Suspend High-Z
Suspend High-Z
Suspend High-Z
Miscellaneous Signals
Core Low
Suspend High-Z
Suspend Low
Immediately
S0/S1
1
after Reset
Low Defined
High High
High High
High High
High High
High High
High High
Running
High-Z High-Z
Low Defined
High-Z (Input) Defined
8
Low High
High-Z High-Z
High High
High-Z Defined
11
High-Z Defined
High-Z Defined
High-Z Defined
High-Z Defined
High-Z Defined
High-Z Defined
Low Defined
High-Z High-Z
Low Defined
S3 S4/S5
Defined Defined
Low Low
Defined Defined
Low Low
High Defined
2
High Defined
Low Low
High-Z Low
Off Off
Off Off
Defined Defined
High-Z High-Z
Off Off
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Off Off
High-Z High-Z
Defined Defined
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