Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 817

Serial Peripheral Interface (SPI)
21.1.10 FREG2—Flash Region 2 (Intel
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base
21.1.11 FREG3—Flash Region 3 (GbE) Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base
Datasheet
SPIBAR + 5Ch
00000000h
Description
SPIBAR + 60h
00000000h
Description
®
ME) Register
Attribute: RO
Size: 32 bits
Attribute: RO
Size: 32 bits
817