Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 468

Bit
7
6
5:4
3
2
1
0
NOTE: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or
SPI. The concept of Feature Space does not apply to SPI-based flash. The PCH simply
decodes these ranges as memory accesses when enabled for the SPI flash interface.
468
BIOS_Legacy_F_EN — R/W. This enables the decoding of the legacy 64KB range at
F0000h – FFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the BIOS
F0000h – FFFFFh
NOTE: The decode for the BIOS legacy F segment is enabled only by this bit and is not
affected by the GEN_PMCON_1.iA64_EN bit.
BIOS_Legacy_E_EN — R/W. This enables the decoding of the legacy 64KB range at
E0000h – EFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the BIOS
E0000h – EFFFFh
NOTE: The decode for the BIOS legacy E segment is enabled only by this bit and is not
affected by the GEN_PMCON_1.iA64_EN bit.
Reserved
BIOS_70_EN — R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
BIOS_60_EN — R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
BIOS_50_EN — R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
BIOS_40_EN — R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
LPC Interface Bridge Registers (D31:F0)
Description
Datasheet