Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 656

Bit
SMI on BAR Enable — R/W.
0 = Disable.
15
1 = Enable. When this bit is 1 and SMI on BAR (D29:F0, D26:F0:6Ch, bit 31) is 1, then
SMI on PCI Command Enable — R/W.
0 = Disable.
14
1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F0, D26:F0:6Ch, bit 30)
SMI on OS Ownership Enable — R/W.
0 = Disable.
13
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F0,
12:6 Reserved
SMI on Async Advance Enable — R/W.
0 = Disable.
5
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F0,
SMI on Host System Error Enable — R/W.
0 = Disable.
4
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F0,
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
3
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F0,
SMI on Port Change Enable — R/W.
0 = Disable.
2
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F0,
SMI on USB Error Enable — R/W.
0 = Disable.
1
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F0, D26:F0:6Ch,
SMI on USB Complete Enable — R/W.
0 = Disable.
0
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F0,
656
the host controller will issue an SMI.
is 1, then the host controller will issue an SMI.
D26:F0:6Ch, bit 29) is 1, the host controller will issue an SMI.
D26:F0:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately.
D26:F0:6Ch, bit 20) is a 1, the host controller will issue an SMI.
D26:F0:6Ch, bit 19) is a 1, the host controller will issue an SMI.
D26:F0:6Ch, bit 18) is a 1, the host controller will issue an SMI.
bit 17) is a 1, the host controller will issue an SMI immediately.
D26:F0:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately.
EHCI Controller Registers (D29:F0, D26:F0)
Description
Datasheet