Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 568

14.1.31 PCS—Port Control and Status Register (SATA–D31:F2)
Address Offset: 92h
Default Value:
Function Level Reset: No
By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled
by software, the ports can transition between the on, partial, and slumber states and
can detect devices. When disabled, the port is in the "off" state and cannot detect any
devices.
If an AHCI-aware or RAID enabled operating system is being booted, then system BIOS
shall insure that all supported SATA ports are enabled prior to passing control to the
OS. Once the AHCI aware OS is booted, it becomes the enabling/disabling policy owner
for the individual SATA ports. This is accomplished by manipulating a port's PxSCTL and
PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of
the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-
boot software must insure that these bits are set to 1 prior to booting the OS,
regardless as to whether or not a device is currently on the port.
Bits
15
14
13
12
11
10
568
93h
–
0000h
OOB Retry Mode (ORM) — R/W.
0 = The SATA controller will not retry after an OOB failure
1 = The SATA controller will continue to retry after an OOB failure until successful
(infinite retry)
Reserved.
Port 5 Present (P5P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P5E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 5 has been detected.
Port 4 Present (P4P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P4E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 4 has been detected.
Port 3 Present (P3P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P3E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 3 has been detected.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Port 2 Present (P2P) — RO. The status of this bit may change at any time. This bit
is cleared when the port is disabled using P2E. This bit is not cleared upon surprise
removal of a device.
0 = No device detected.
1 = The presence of a device on Port 2 has been detected.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
SATA Controller Registers (D31:F2)
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet