Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 754

18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 0Fh
Default Value:
Note: This register is in the resume well and is reset by RSMRST#.
Bit
7:3 Reserved
SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
2
0 = The PCH drives the SMBCLK pin low, independent of what the other SMB logic
SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent
on an external signal level. This pin returns the value on the SMBDATA pin. This allows
software to read the current state of the pin.
1
0 = Low
1 = High
SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBCLK pin. This allows
software to read the current state of the pin.
0
0 = Low
1 = High
18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 10h
Default Value:
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
Bit
7:1 Reserved
HOST_NOTIFY_STS — R/WC. The PCH sets this bit to a 1 when it has completely
received a successful Host Notify Command on the SMBus pins. Software reads this bit
to determine that the source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any information needed from
0
the Notify address and data registers by writing a 1 to this bit. Note that the PCH will
allow the Notify Address and Data registers to be over-written once this bit has been
cleared. When this bit is 1, the PCH will NACK the first byte (host address) of any new
"Host Notify" commands on the SMBus pins. Writing a 0 to this bit has no effect.
754
See below
the pin.
would otherwise indicate for the SMBCLK pin. (Default)
00h
SMBus Controller Registers (D31:F3)
Attribute: R/W, RO
Size: 8 bits
Description
Attribute: R/WC
Size: 8 bits
Description
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