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DMA internal
address
DMA control
DMA register
operation
Note:
The lower word of MAR is the updated value after the operation in [1].
Figure 7.28 Contention between DMAC Register Update and CPU Read
7.6.2
Module Stop
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
•
Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
7.6.3
Medium-Speed Mode
When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-
detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip
peripheral modules operate on a high-speed clock.
Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or
another DMAC channel, and the next interrupt is generated, is less than one state with respect to
the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be
ignored.
7.6.4
Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ signal falling
edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt
request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low
level that occurs before execution of the DMABCRL write to enable transfer.
CPU longword read
MAR upper
MAR lower
word read
word read
Transfer
source
Idle
Read
[1]
DMA transfer cycle
DMA read
DMA write
Transfer
destination
Write
Idle
[2]
Rev. 3.0, 10/02, page 193 of 686
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