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H'FFF2: IRQ Status Register IRQR: Interrupt Controller
Bit
:
7
0
Initial value
:
R/W
:
IRQ5 to IRQ0 flag
0
[Clearing conditions]
Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
When IRQn interrupt exception handling is executed
1
[Setting conditions]
(1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0)
(2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0)
(3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1)
Note: * Only 0 can be written to clear the flag.
H'FFF3: Interrupt Control Register A ICRA: Interrupt Controller
H'FFF4: Interrupt Control Register B ICRB: Interrupt Controller
H'FFF5: Interrupt Control Register C ICRC: Interrupt Controller
H'FFF6: Interrupt Control Register D ICRD: Interrupt Controller
Bit
:
ICR7
Initial value
:
R/W
:
R/W
Interrupt control level
Rev. 1.0, 02/00, page 1112 of 1141
6
5
IRQ5F
0
0
R/(W)*
7
6
ICR6
ICR5
0
0
R/W
R/W
0
Corresponding interrupt source is control level 0 (non-priority)
1
Corresponding interrupt source is control level 1 (priority)
4
3
IRQ4F
IRQ3F
0
0
R/(W)*
R/(W)*
5
4
ICR4
ICR3
0
0
R/W
R/W
2
1
IRQ2F
IRQ1F
0
0
R/(W)*
R/(W)*
3
2
ICR2
ICR1
0
0
R/W
R/W
0
IRQ0F
0
R/(W)*
(Initial value)
(n = 5 to 0)
1
0
ICR0
0
0
R/W
(Initial value)
(n = 7 to 0)
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