Hitachi H8S/2199 Hardware Manual page 1111

H'FFEB: Low-Power Control Register LPWRCR: System Control
7
Bit :
DTON
0
Initial value :
R/W :
R/W
Direct transfer on flag
0
1
6 5
LSON NESEL
0 0
R/W R/W
Noise elimination sampling frequency select
0
1
Low-speed on flag
0 • When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• After watch mode is cleared, a transition is made to high-speed mode
1 • When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode, subactive mode, sleep mode or standby mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode.
• After watch mode is cleared, a transition is made to subactive mode
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
directily to high-speed mode, or a transition is made to subsleep mode
4 3 2
— — —
0 0 0
— — —
Subactive mode clock select
SA1 SA0
Operating clock of CPU is φw/8
0 0
Operating clock of CPU is φw/4
0 1
Operating clock of CPU is φw/2
1 *
Note: * Don't care.
Sampling at φ divided by 16
Sampling at φ divided by 4
1 0
SA1 SA0
0 0
R/W R/W
Subactive mode clock select
Rev. 1.0, 02/00, page 1109 of 1141