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H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller
Bit
:
Initial value :
R/W
:
IRQ0 pin detected dege select bits
IRQ0EG1
0
0
1
Note: * Don't care.
IRQ5 to IRQ1 pins detected edge select bits
0
Interrupt request generated at falling edge of IRQn pin input
1
Interrupt request generated at rising edge of IRQn pin input
H'FFF1: IRQ Enable Register IENR: Interrupt Controller
Bit
:
Initial value
:
R/W
:
7
6
IRQ5EG
IRQ4EG
0
0
R/W
IRQ0EG0
0
Interrupt request generaed at falling edge of IRQ0 pin input
1
Interrupt request generaed at rising edge of IRQ0 pin input
*
Interrupt request generaed at bath falling and rising edge of IRQ0 pin input
7
6
IRQ5E
0
0
R/W
5
4
IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG2
0
0
R/W
R/W
R/W
Description
5
4
IRQ4E
IRQ3E
0
0
R/W
R/W
IRQ5 to IRQ0 enable bits
0
IRQn interrupt is disabled
IRQn interrupt is enabled
1
3
2
1
0
0
0
R/W
R/W
(Initial value)
(n = 5 to 1)
3
2
IRQ2E
IRQ1E
0
0
R/W
R/W
(Initial value)
Rev. 1.0, 02/00, page 1111 of 1141
0
0
R/W
(Initial value)
1
0
IRQ0E
0
0
R/W
(n = 5 to 0)
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