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Hitachi H8S/2215 Series Manuals
Manuals and User Guides for Hitachi H8S/2215 Series. We have
1
Hitachi H8S/2215 Series manual available for free PDF download: Hardware Manual
Hitachi H8S/2215 Series Hardware Manual (745 pages)
Hitachi Single-Chip Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 3.4 MB
Table of Contents
Table of Contents
29
Section 1 Overview
59
Overview
59
Section 1 Overview
60
Figure 1.1 Internal Block Diagram
60
Internal Block Diagram
60
Figure 1.2 Pin Arrangement (TFP-120)
61
Pin Arrangement
61
Figure 1.3 Pin Arrangement (BP-112)
62
Pin Functions in each Operating Mode
63
Pin Functions
68
Features
77
Differences between H8S/2600 CPU and H8S/2000 CPU
78
Section 2 CPU
77
Section 2 CPU
78
Differences from H8/300 CPU
79
Differences from H8/300H CPU
79
CPU Operating Modes
80
Normal Mode
80
Advanced Mode
81
Figure 2.1 Exception Vector Table (Normal Mode)
81
Figure 2.2 Stack Structure in Normal Mode
81
Figure 2.3 Exception Vector Table (Advanced Mode)
82
Figure 2.4 Stack Structure in Advanced Mode
83
Address Space
84
Figure 2.5 Memory Map
84
Register Configuration
85
Figure 2.6 CPU Registers
85
Figure 2.7 Usage of General Registers
86
General Registers
86
Extended Control Register (EXR)
87
Figure 2.8 Stack
87
Program Counter (PC)
87
Condition-Code Register (CCR)
88
Initial Register Values
90
Data Formats
90
General Register Data Formats
90
Figure 2.9 General Register Data Formats (1)
90
Figure 2.9 General Register Data Formats (2)
91
Memory Data Formats
92
Figure 2.10 Memory Data Formats
92
Instruction Set
93
Table 2.1 Instruction Classification
93
Table 2.2 Operation Notation
94
Table of Instructions Classified by Function
94
Table 2.3 Data Transfer Instructions
95
Table 2.4 Arithmetic Operations Instructions (1)
96
Table 2.4 Arithmetic Operations Instructions (2)
97
Table 2.5 Logic Operations Instructions
98
Table 2.6 Shift Instructions
98
Table 2.7 Bit Manipulation Instructions (1)
99
Table 2.7 Bit Manipulation Instructions (2)
100
Table 2.8 Branch Instructions
101
Table 2.9 System Control Instruction
102
Basic Instruction Formats
103
Table 2.10 Block Data Transfer Instruction
103
Addressing Modes and Effective Address Calculation
104
Figure 2.11 Instruction Formats (Examples)
104
Table 2.11 Addressing Modes
104
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
105
Register Direct-Rn
105
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
105
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
105
Register Indirect-@Ern
105
Immediate-#XX:8, #XX:16, or #XX:32
106
Memory Indirect-@@Aa:8
106
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
106
Table 2.12 Absolute Address Access Ranges
106
Effective Address Calculation
107
Figure 2.12 Branch Address Specification in Memory Indirect Mode
107
Table 2.13 Effective Address Calculation (1)
108
Table 2.13 Effective Address Calculation (2)
109
Processing States
110
Usage Notes
111
Note on TAS Instruction Usage
111
STM/LTM Instruction Usage
111
Figure 2.13 State Transitions
111
Note on Bit Manipulation Instructions
112
Section 3 MCU Operating Modes
113
Section 3 MCU Operating Modes
113
Operating Mode Selection
113
Table 3.1 MCU Operating Mode Selection
113
Register Descriptions
114
Mode Control Register (MDCR)
114
System Control Register (SYSCR)
115
Operating Mode Descriptions
116
Mode 4
116
Mode 5
116
Mode 6
117
Mode 7
117
Pin Functions
117
Table 3.2 Pin Functions in each Operating Mode
118
Section 3 MCU Operating Modes
119
Memory Map in each Operating Mode
119
Figure 3.1 Memory Map in each Operating Mode for HD64F2215, HD64F2215U, and
119
Figure 3.2 Memory Map in each Operating Mode for HD6432215B
120
Figure 3.3 Memory Map in each Operating Mode for HD6432215C
121
Section 4 Exception Handling
123
Exception Handling Types and Priority
123
Exception Sources and Exception Vector Table
123
Section 4 Exception Handling
124
Table 4.2 Exception Handling Vector Table
124
Reset
125
Reset Types
125
Table 4.3 Reset Types
125
Reset Exception Handling
126
Figure 4.1 Reset Sequence (Modes 2 and 3: Not Available in this LSI)
126
Interrupts after Reset
127
State of On-Chip Peripheral Modules after Reset Release
127
Figure 4.2 Reset Sequence (Mode 4)
127
Traces
128
Interrupts
128
Table 4.4 Status of CCR and EXR after Trace Exception Handling
128
Trap Instruction
129
Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling
129
Stack Status after Exception Handling
130
Section 4 Exception Handling
130
Figure 4.3 Stack Status after Exception Handling
130
Notes on Use of the Stack
131
Figure 4.4 Operation When SP Value Is Odd
131
Section 5 Interrupt Controller
133
Features
133
Section 5 Interrupt Controller
134
Figure 5.1 Block Diagram of Interrupt Controller
134
Section 5 Interrupt Controller
135
Input/Output Pins
135
Register Descriptions
135
Table 5.1 Pin Configuration
135
Interrupt Priority Registers a to G, I to K, M (IPRA to IPRG, IPRI to IPRK, IPRM)
136
IRQ Enable Register (IER)
137
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
138
IRQ Status Register (ISR)
140
Interrupt Sources
141
External Interrupts
141
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
141
Internal Interrupts
142
Interrupt Exception Handling Vector Table
142
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
143
Interrupt Control Modes and Interrupt Operation
145
Interrupt Control Mode 0
145
Table 5.3 Interrupt Control Modes
145
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
146
Interrupt Control Mode 2
147
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 2
148
Interrupt Exception Handling Sequence
149
Figure 5.5 Interrupt Exception Handling
149
Interrupt Response Times
150
Table 5.4 Interrupt Response Times
150
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses
150
DTC Activation by Interrupt
151
Figure 5.6 Interrupt Control for DTC and DMAC
151
Usage Notes
153
Contention between Interrupt Generation and Disabling
153
Table 5.6 Interrupt Source Selection and Clearing Control
153
Instructions that Disable Interrupts
154
Times When Interrupts Are Disabled
154
Interrupts During Execution of EEPMOV Instruction
154
Figure 5.7 Contention between Interrupt Generation and Disabling
154
Section 6 Bus Controller
157
Features
157
Section 6 Bus Controller
158
Figure 6.1 Block Diagram of Bus Controller
158
Section 6 Bus Controller
159
Input/Output Pins
159
Register Descriptions
159
Bus Width Control Register (ABWCR)
159
Table 6.1 Pin Configuration
159
Access State Control Register (ASTCR)
160
Wait Control Registers H and L (WCRH, WCRL)
161
Bus Control Register H (BCRH)
165
Bus Control Register L (BCRL)
166
Pin Function Control Register (PFCR)
167
Bus Control
168
Area Divisions
168
Figure 6.2 Overview of Area Divisions
168
Bus Specifications
169
Bus Interface for each Area
170
Table 6.2 Bus Specifications for each Area (Basic Bus Interface)
170
Chip Select Signals
171
Figure 6.3 Csn Signal Output Timing (N = 0 to 7)
171
Basic Timing
172
On-Chip Memory (ROM, RAM) Access Timing
172
Figure 6.4 On-Chip Memory Access Cycle
172
On-Chip Peripheral Module Access Timing
173
Figure 6.5 Pin States During On-Chip Memory Access
173
Figure 6.6 On-Chip Peripheral Module Access Cycle
173
External Address Space Access Timing
174
Figure 6.7 Pin States During On-Chip Peripheral Module Access
174
Basic Bus Interface
175
Data Size and Data Alignment
175
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)
175
Valid Strobes
176
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
176
Table 6.3 Data Buses Used and Valid Strobes
176
Basic Timing
177
Figure 6.10 Bus Timing for 8-Bit 2-State Access Space
177
Figure 6.11 Bus Timing for 8-Bit 3-State Access Space (Except Area 6)
178
Figure 6.12 Bus Timing for Area 6
179
Figure 6.13 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
180
Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
181
Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
182
Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
183
Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
184
Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
185
Wait Control
186
Figure 6.19 Example of Wait State Insertion Timing
187
Burst ROM Interface
188
Basic Timing
188
Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
189
Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
189
Wait Control
190
Idle Cycle
191
Figure 6.22 Example of Idle Cycle Operation (1)
191
Figure 6.23 Example of Idle Cycle Operation (2)
192
Figure 6.24 Relationship between Chip Select (CS) and Read (RD)
192
Table 6.4 Pin States in Idle Cycle
193
Bus Release
194
Table 6.5 Pin States in Bus Released State
194
Figure 6.25 Bus-Released State Transition Timing
195
Bus Arbitration
196
Operation
196
Bus Transfer Timing
196
External Bus Release Usage Note
197
Resets and the Bus Controller
197
Section 7 DMA Controller
199
Features
199
Section 7 DMA Controller
200
Figure 7.1 Block Diagram of DMAC
200
Section 7 DMA Controller
201
Register Configuration
201
Table7.1 Short Address Mode and Full Address Mode (for 1 Channel: Example of Channel 0)
201
Register Descriptions
203
Memory Address Registers (MAR)
203
I/O Address Register (IOAR)
203
Execute Transfer Count Register (ETCR)
204
DMA Control Register (DMACR)
205
DMA Band Control Register (DMABCR)
211
DMA Write Enable Register (DMAWER)
219
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
219
Operation
221
Transfer Modes
221
Table 7.2 DMAC Transfer Modes
221
Sequential Mode
222
Table 7.3 Register Functions in Sequential Mode
222
Figure 7.3 Operation in Sequential Mode
223
Figure 7.4 Example of Sequential Mode Setting Procedure
224
Idle Mode
225
Figure 7.5 Operation in Idle Mode
225
Table 7.4 Register Functions in Idle Mode
225
Repeat Mode
226
Figure 7.6 Example of Idle Mode Setting Procedure
226
Table 7.5 Register Functions in Repeat Mode
227
Figure 7.7 Operation in Repeat Mode
228
Figure 7.8 Example of Repeat Mode Setting Procedure
229
Normal Mode
230
Table 7.6 Register Functions in Normal Mode
230
Figure 7.9 Operation in Normal Mode
231
Figure 7.10 Example of Normal Mode Setting Procedure
232
Block Transfer Mode
233
Table 7.7 Register Functions in Block Transfer Mode
233
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0)
234
Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1)
235
Figure 7.13 Operation Flow in Block Transfer Mode
236
Figure 7.14 Example of Block Transfer Mode Setting Procedure
237
DMAC Activation Sources
238
Table 7.8 DMAC Activation Sources
238
Basic DMAC Bus Cycles
239
Figure 7.15 Example of DMA Transfer Bus Timing
239
DMAC Bus Cycles (Dual Address Mode)
240
Figure 7.16 Example of Short Address Mode Transfer
240
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer
241
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer
241
Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer
242
Figure 7.20 Example of DREQ Level Activated Normal Mode Transfer
243
DMAC Multi-Channel Operation
244
Figure 7.21 Example of DREQ Level Activated Block Transfer Mode Transfer
244
Relation between the DMAC, External Bus Requests, Refresh Cycles, and the DTC
245
Figure 7.22 Example of Multi-Channel Transfer
245
Table 7.9 DMAC Channel Priority Order
245
NMI Interrupts and DMAC
246
Figure 7.23 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt
246
Forced Termination of DMAC Operation
247
Clearing Full Address Mode
247
Figure 7.24 Example of Procedure for Forcibly Terminating DMAC Operation
247
Figure 7.25 Example of Procedure for Clearing Full Address Mode
248
Interrupts
249
Figure 7.26 Block Diagram of Transfer End/Transfer Break Interrupt
249
Table 7.10 Interrupt Source Priority Order
249
Usage Notes
250
DMAC Register Access During Operation
250
Figure 7.27 DMAC Register Update Timing
250
Module Stop
251
Medium-Speed Mode
251
Activation Source Acceptance
251
Figure 7.28 Contention between DMAC Register Update and CPU Read
251
Internal Interrupt after End of Transfer
252
Channel Re-Setting
252
Section 8 Data Transfer Controller (DTC)
253
Features
253
Section 8 Data Transfer Controller (DTC)
254
Register Descriptions
254
Figure 8.1 Block Diagram of DTC
254
DTC Mode Register a (MRA)
255
DTC Destination Address Register (DAR)
256
DTC Mode Register B (MRB)
256
DTC Source Address Register (SAR)
256
DTC Transfer Count Register a (CRA)
256
DTC Enable Registers (DTCERA to DTCERF)
257
DTC Transfer Count Register B (CRB)
257
DTC Vector Register (DTVECR)
258
Section 8 Data Transfer Controller (DTC)
259
Activation Sources
259
Section 2 CPU
259
Figure 8.2 Block Diagram of DTC Activation Source Control
259
Table 8.1 Activation Source and DTCER Clearance
259
Location of Register Information and DTC Vector Table
260
Figure 8.3 Correspondence between DTC Vector Address and Register Information
260
Figure 8.4 Correspondence between DTC Vector Address and Register Information
261
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCE
262
Operation
263
Figure 8.5 Flowchart of DTC Operation
263
Normal Mode
264
Table 8.3 Overview of DTC Functions
264
Figure 8.6 Memory Mapping in Normal Mode
265
Table 8.4 Register Information in Normal Mode
265
Figure 8.7 Memory Mapping in Repeat Mode
266
Repeat Mode
266
Table 8.5 Register Information in Repeat Mode
266
Block Transfer Mode
267
Figure 8.8 Memory Mapping in Block Transfer Mode
267
Table 8.6 Register Information in Block Transfer Mode
267
Chain Transfer
268
Figure 8.9 Chain Transfer Memory Map
268
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
269
Interrupts
269
Operation Timing
269
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
270
Figure 8.12 DTC Operation Timing (Example of Chain Transfer)
270
Number of DTC Execution States
270
Table 8.7 DTC Execution Status
271
Table 8.8 Number of States Required for each Execution Status
271
Procedures for Using DTC
272
Activation by Interrupt
272
Activation by Software
272
Examples of Use of the DTC
273
Normal Mode
273
Software Activation
273
Usage Notes
274
Module Stop
274
On-Chip RAM
274
DTCE Bit Setting
274
DMAC Transfer End Interrupt
274
Section 9 I/O Ports
275
Section 9 I/O Ports
276
Table 9.1 Port Functions (2)
276
Table 9.1 Port Functions (3)
277
Table 9.1 Port Functions (4)
278
Port 1
279
Port 1 Data Direction Register (P1DDR)
279
Port 1 Data Register (P1DR)
279
Port 1 Register (PORT1)
280
Pin Functions
280
Table 9.2 P17 Pin Function
280
Table 9.3 P16 Pin Function
280
Table 9.4 P15 Pin Function
281
Table 9.5 P14 Pin Function
281
Table 9.6 P13 Pin Function
281
Port 3
282
Table 9.7 P12 Pin Function
282
Table 9.8 P11 Pin Function
282
Table 9.9 P10 Pin Function
282
Port 3 Data Direction Register (P3DDR)
283
Port 3 Data Register (P3DR)
283
Port 3 Open-Drain Control Register (P3ODR)
284
Port 3 Register (PORT3)
284
Pin Functions
285
Table 9.10 P36 Pin Function
285
Table 9.11 P35 Pin Function
285
Table 9.12 P34 Pin Function
285
Table 9.13 P33 Pin Function
285
Table 9.14 P32 Pin Function
285
Port 4
286
Port 4 Register (PORT4)
286
Pin Function
286
Table 9.15 P31 Pin Function
286
Table 9.16 P30 Pin Function
286
Port 7
287
Port 7 Data Direction Register (P7DDR)
287
Port 7 Data Register (P7DR)
287
Port 7 Register (PORT7)
288
Pin Functions
288
Table 9.17 P74 Pin Function
288
Table 9.18 P73 Pin Function
288
Table 9.19 P72 Pin Function
289
Table 9.20 P71 Pin Function
289
Table 9.21 P70 Pin Function
289
Port 9
290
Port 9 Register (PORT9)
290
Pin Function
290
Port a
290
Port a Data Direction Register (PADDR)
291
Port a Data Register (PADR)
291
Port a Register (PORTA)
292
Port a MOS Pull-Up Control Register (PAPCR)
292
Port a Open Drain Control Register (PAODR)
293
Pin Functions
293
Table 9.22 PA3 Pin Function
293
Table 9.23 PA2 Pin Function
294
Table 9.24 PA1 Pin Function
294
Table 9.25 PA0 Pin Function
294
Port a Input Pull-Up MOS Function
295
Port B
295
Table 9.26 Input Pull-Up MOS States (Port A)
295
Port B Data Direction Register (PBDDR)
296
Port B Data Register (PBDR)
296
Port B MOS Pull-Up Control Register (PBPCR)
297
Port B Register (PORTB)
297
Pin Functions
298
Table 9.27 PB7 Pin Function
298
Table 9.28 PB6 Pin Function
298
Table 9.29 PB5 Pin Function
298
Table 9.30 PB4 Pin Function
298
Port B Input Pull-Up MOS Function
299
Table 9.31 PB3 Pin Function
299
Table 9.32 PB2 Pin Function
299
Table 9.33 PB1 Pin Function
299
Table 9.34 PB0 Pin Function
299
Table 9.35 Input Pull-Up MOS States (Port B)
300
Port C
301
Port C Data Direction Register (PCDDR)
301
Port C Data Register (PCDR)
301
Port C Register (PORTC)
302
Port C Pull-Up MOS Control Register (PCPCR)
302
Pin Functions
302
Table 9.36 PC7 Pin Function
302
Table 9.37 PC6 Pin Function
303
Table 9.38 PC5 Pin Function
303
Table 9.39 PC4 Pin Function
303
Table 9.40 PC3 Pin Function
303
Table 9.41 PC2 Pin Function
303
Table 9.42 PC1 Pin Function
303
Port C Input Pull-Up MOS Function
304
Port D
304
Table 9.43 PC0 Pin Function
304
Table 9.44 Input Pull-Up MOS States (Port C)
304
Port D Data Direction Register (PDDDR)
305
Port D Data Register (PDDR)
305
Pin Functions
306
Port D Pull-Up MOS Control Register (PDPCR)
306
Port D Register (PORTD)
306
Table 9.45 PD7 Pin Function
307
Table 9.46 PD6 Pin Function
307
Table 9.47 PD5 Pin Function
307
Table 9.48 PD4 Pin Function
307
Table 9.49 PD3 Pin Function
307
Table 9.50 PD2 Pin Function
307
Port D Input Pull-Up MOS Function
308
Port E
308
Table 9.51 PD1 Pin Function
308
Table 9.52 PD0 Pin Function
308
Table 9.53 Input Pull-Up MOS States (Port D)
308
Port E Data Direction Register (PEDDR)
309
Port E Data Register (PEDR)
309
Port E Pull-Up MOS Control Register (PEPCR)
310
Port E Register (PORTE)
310
Pin Functions
311
Table 9.54 PE7 Pin Function
311
Table 9.55 PE6 Pin Function
311
Table 9.56 PE5 Pin Function
311
Table 9.57 PE4 Pin Function
311
Port E Input Pull-Up MOS State
312
Table 9.58 PE3 Pin Function
312
Table 9.59 PE2 Pin Function
312
Table 9.60 PE1 Pin Function
312
Table 9.61 PE0 Pin Function
312
Port F
313
Table 9.62 Input Pull-Up MOS States (Port E)
313
Port F Data Direction Register (PFDDR)
314
Port F Data Register (PFDR)
314
Pin Functions
315
Port F Register (PORTF)
315
Table 9.63 PF7 Pin Function
315
Table 9.64 PF6 Pin Function
315
Table 9.65 PF5 Pin Function
315
Table 9.66 PF4 Pin Function
316
Table 9.67 PF3 Pin Function
316
Table 9.68 PF2 Pin Function
316
Table 9.69 PF1 Pin Function
316
Port G
317
Port G Data Direction Register
317
Table 9.70 PF0 Pin Function
317
Port G Data Register
318
Port G Register (PORTG)
318
Pin Functions
318
Table 9.71 PG4 Pin Function
318
Table 9.72 PG3 Pin Function
319
Table 9.73 PG2 Pin Function
319
Table 9.74 PG1 Pin Function
319
Table 9.75 PG0 Pin Function
319
Section 10 16-Bit Timer Pulse Unit (TPU)
321
Features
321
Section 10 16-Bit Timer Pulse Unit (TPU)
322
Figure 10.1 Block Diagram of TPU
322
Section 10 16-Bit Timer Pulse Unit (TPU)
323
Table 10.1 TPU Functions
323
Input/Output Pins
325
Table 10.2 Pin Configuration
325
Register Descriptions
326
Timer Control Register (TCR)
327
Table 10.3 CCLR2 to CCLR0 (Channel 0)
328
Table 10.4 CCLR2 to CCLR0 (Channels 1 and 2)
328
Table 10.5 TPSC2 to TPSC0 (Channel 0)
329
Table 10.6 TPSC2 to TPSC0 (Channel 1)
329
Table 10.7 TPSC2 to TPSC0 (Channel 2)
330
Timer Mode Register (TMDR)
331
Timer I/O Control Register (TIOR)
332
Table 10.8 MD3 to MD0
332
Table 10.9 TIORH_0 (Channel 0)
334
Table 10.10 TIORH_0 (Channel 0)
335
Table 10.11 TIORL_0 (Channel 0)
336
Table 10.12 TIORL_0 (Channel 0)
337
Table 10.13 TIOR_1 (Channel 1)
338
Table 10.14 TIOR_1 (Channel 1)
339
Table 10.15 TIOR_2 (Channel 2)
340
Table 10.16 TIOR_2 (Channel 2)
341
Timer Interrupt Enable Register (TIER)
342
Timer Status Register (TSR)
344
Timer Counter (TCNT)
346
Timer General Register (TGR)
346
Timer Start Register (TSTR)
347
Timer Synchro Register (TSYR)
348
Interface to Bus Master
349
16-Bit Registers
349
Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]
349
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
349
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
350
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
350
Operation
351
Basic Functions
351
Figure 10.6 Example of Counter Operation Setting Procedure
351
Figure 10.7 Free-Running Counter Operation
352
Figure 10.8 Periodic Counter Operation
352
Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match
353
Figure 10.10 Example of 0 Output/1 Output Operation
353
Figure 10.11 Example of Toggle Output Operation
354
Figure 10.12 Example of Input Capture Operation Setting Procedure
354
Synchronous Operation
355
Figure 10.13 Example of Input Capture Operation
355
Figure 10.14 Example of Synchronous Operation Setting Procedure
356
Buffer Operation
357
Figure 10.15 Example of Synchronous Operation
357
Figure 10.16 Compare Match Buffer Operation
357
Table 10.17 Register Combinations in Buffer Operation
357
Figure 10.17 Input Capture Buffer Operation
358
Figure 10.18 Example of Buffer Operation Setting Procedure
358
Figure 10.19 Example of Buffer Operation (1)
359
Figure 10.20 Example of Buffer Operation (2)
359
PWM Modes
360
Table 10.18 PWM Output Registers and Output Pins
360
Figure 10.21 Example of PWM Mode Setting Procedure
361
Figure 10.22 Example of PWM Mode Operation (1)
361
Figure 10.23 Example of PWM Mode Operation (2)
362
Phase Counting Mode
363
Figure 10.24 Example of PWM Mode Operation (3)
363
Figure 10.25 Example of Phase Counting Mode Setting Procedure
364
Table 10.19 Phase Counting Mode Clock Input Pins
364
Figure 10.26 Example of Phase Counting Mode 1 Operation
365
Table 10.20 Up/Down-Count Conditions in Phase Counting Mode 1
365
Figure 10.27 Example of Phase Counting Mode 2 Operation
366
Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 2
366
Figure 10.28 Example of Phase Counting Mode 3 Operation
367
Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 3
367
Figure 10.29 Example of Phase Counting Mode 4 Operation
368
Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4
368
Interrupts
369
Interrupt Source and Priority
369
Table 10.24 TPU Interrupts
369
DTC Activation
370
DMAC Activation
370
A/D Converter Activation
370
Operation Timing
371
Input/Output Timing
371
Figure 10.30 Count Timing in Internal Clock Operation
371
Figure 10.31 Count Timing in External Clock Operation
371
Figure 10.32 Output Compare Output Timing
372
Figure 10.33 Input Capture Input Signal Timing
372
Figure 10.34 Counter Clear Timing (Compare Match)
373
Figure 10.35 Counter Clear Timing (Input Capture)
373
Figure 10.36 Buffer Operation Timing (Compare Match)
373
Interrupt Signal Timing
374
Figure 10.37 Buffer Operation Timing (Input Capture)
374
Figure 10.38 TGI Interrupt Timing (Compare Match)
374
Figure 10.39 TGI Interrupt Timing (Input Capture)
375
Figure 10.40 TCIV Interrupt Setting Timing
375
Figure 10.41 TCIU Interrupt Setting Timing
376
Figure 10.42 Timing for Status Flag Clearing by CPU
376
Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation
377
Usage Notes
378
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
378
Figure 10.45 Contention between TCNT Write and Clear Operations
379
Figure 10.46 Contention between TCNT Write and Increment Operations
379
Figure 10.47 Contention between TGR Write and Compare Match
380
Figure 10.48 Contention between Buffer Register Write and Compare Match
380
Figure 10.49 Contention between TGR Read and Input Capture
381
Figure 10.50 Contention between TGR Write and Input Capture
381
Figure 10.51 Contention between Buffer Register Write and Input Capture
382
Figure 10.52 Contention between Overflow and Counter Clearing
382
Figure 10.53 Contention between TCNT Write and Overflow
383
Section 11 8-Bit Timers (TMR)
385
Features
385
Section 11 8-Bit Timers (TMR)
386
Figure 11.1 Block Diagram of 8-Bit Timer
386
Section 11 8-Bit Timers (TMR)
387
Input/Output Pins
387
Register Descriptions
387
Timer Counters (TCNT)
387
Time Constant Registers a (TCORA)
387
Time Constant Registers B (TCORB)
387
Time Control Registers (TCR)
387
Table 11.1 Pin Configuration
387
Timer Control/Status Registers (TCSR)
390
Table 11.2 Clock Input to TCNT and Count Condition
390
Operation
392
Pulse Output
392
Figure 11.2 Example of Pulse Output
392
Operation Timing
393
TCNT Incrementation Timing
393
Figure 11.3 Count Timing for Internal Clock Input
393
Figure 11.4 Count Timing for External Clock Input
393
Setting of Compare Match Flags CMFA and CMFB
394
Timer Output Timing
394
Timing of Compare Match Clear
394
Figure 11.5 Timing of CMF Setting
394
Figure 11.6 Timing of Timer Output
394
Timing of TCNT External Reset
395
Figure 11.7 Timing of Compare Match Clear
395
Figure 11.8 Timing of Clearance by External Reset
395
Timing of Overflow Flag (OVF) Setting
396
Figure 11.9 Timing of OVF Setting
396
Operation with Cascaded Connection
397
16-Bit Counter Mode
397
Compare Match Count Mode
397
Interrupts
398
Interrupt Sources and DTC Activation
398
A/D Converter Activation
398
Table 11.3 8-Bit Timer Interrupt Sources
398
Usage Notes
399
Contention between TCNT Write and Clear
399
Figure 11.10 Contention between TCNT Write and Clear
399
Contention between TCNT Write and Increment
400
Figure 11.11 Contention between TCNT Write and Increment
400
Contention between TCOR Write and Compare Match
401
Figure 11.12 Contention between TCOR Write and Compare Match
401
Contention between Compare Matches a and B
402
Switching of Internal Clocks and TCNT Operation
402
Table 11.4 Timer Output Priorities
402
Table 11.5 Switching of Internal Clock and TCNT Operation
403
Mode Setting with Cascaded Connection
404
Section 12 Watchdog Timer
405
Features
405
Figure 12.1 Block Diagram of WDT
405
Register Descriptions
406
Timer Counter (TCNT)
406
Timer Control/Status Register (TCSR)
406
Reset Control/Status Register (RSTCSR)
408
Operation
409
Watchdog Timer Mode
409
Figure 12.2 Operation in Watchdog Timer Mode
409
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
410
Figure 12.3 Timing of WOVF Setting
410
Interval Timer Mode
411
Timing of Setting of Overflow Flag (OVF)
411
Figure 12.4 Operation in Interval Timer Mode
411
Figure 12.5 Timing of OVF Setting
411
Section 12 Watchdog Timer
412
Interrupts
412
Usage Notes
412
Notes on Register Access
412
Figure 12.6 Format of Data Written to TCNT and TCSR
412
Table 12.1 WDT Interrupt Source
412
Contention between Timer Counter (TCNT) Write and Increment
413
Figure 12.7 Format of Data Written to RSTCSR (Example of WDT0)
413
Changing Value of CKS2 to CKS0
414
Switching between Watchdog Timer Mode and Interval Timer Mode
414
Internal Reset in Watchdog Timer Mode
414
Figure 12.8 Contention between TCNT Write and Increment
414
Section 13 Serial Communication Interface
415
Features
415
Block Diagram
416
Figure 13.1 Block Diagram of SCI_0
417
Figure 13.2 Block Diagram of SCI_1 and SCI_2
418
Section 13 Serial Communication Interface
419
Input/Output Pins
419
Register Descriptions
419
Receive Shift Register (RSR)
419
Table 13.1 Pin Configuration
419
Receive Data Register (RDR)
420
Transmit Data Register (TDR)
420
Transmit Shift Register (TSR)
420
Serial Mode Register (SMR)
421
Serial Control Register (SCR)
423
Serial Status Register (SSR)
425
Smart Card Mode Register (SCMR)
428
Serial Extended Mode Register 0 (SEMR_0)
429
Figure 13.3 Examples of Base Clock When Average Transfer Rate Is Selected
431
Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input
432
Bit Rate Register (BRR)
433
Table 13.2 Relationships between the N Setting in BRR and Bit Rate B
433
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
434
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
435
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
436
Table 13.4 Maximum Bit Rate for each Frequency (Asynchronous Mode)
436
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
437
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
438
Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
438
Operation in Asynchronous Mode
439
Data Transfer Format
439
Figure 13.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
439
Table 13.8 Serial Transfer Formats (Asynchronous Mode)
440
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
441
Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode
441
Clock
442
SCI Initialization (Asynchronous Mode)
442
Figure 13.7 Relationship between Output Clock and Transfer Data Phase
442
(Asynchronous Mode)
442
Data Transmission (Asynchronous Mode)
443
Figure 13.8 Sample SCI Initialization Flowchart
443
Figure 13.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
444
Figure 13.10 Sample Serial Transmission Flowchart
445
Serial Data Reception (Asynchronous Mode)
446
Table 13.9 SSR Status Flags and Receive Data Handling
447
Figure 13.12 Sample Serial Reception Data Flowchart (1)
448
Multiprocessor Communication Function
449
Figure 13.12 Sample Serial Reception Data Flowchart (2)
449
Figure 13.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
450
Multiprocessor Serial Data Transmission
450
Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart
451
Figure 13.11 Example of SCI Operation in Reception
452
Figure 13.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
452
Multiprocessor Serial Data Reception
452
Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1)
453
Operation in Clocked Synchronous Mode
454
Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2)
454
Clock
455
Figure 13.17 Data Format in Synchronous Communication (for LSB-First)
455
SCI Initialization (Clocked Synchronous Mode)
455
Figure 13.18 Sample SCI Initialization Flowchart
456
Serial Data Transmission (Clocked Synchronous Mode)
456
Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode
457
Figure 13.20 Sample Serial Transmission Flowchart
458
Serial Data Reception (Clocked Synchronous Mode)
458
Figure 13.21 Example of SCI Operation in Reception
459
Figure 13.22 Sample Serial Reception Flowchart
460
Simultaneous Serial Data Transmission and Reception
461
(Clocked Synchronous Mode)
461
Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
462
SCI Select Function
463
Figure 13.24 Example of Communication Using the SCI Select Function
464
Figure 13.25 Operation of Communication Using the SCI Select Function
465
Interrupts
466
Interrupts in Normal Serial Communication Interface Mode
466
Usage Notes
467
Break Detection and Processing (Asynchronous Mode Only)
467
Mark State and Break Detection (Asynchronous Mode Only)
467
Table 13.10 SCI Interrupt Sources
467
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
468
Restrictions on Use of DMAC or DTC
468
Operation in Case of Mode Transition
468
Figure 13.26 Example of Clocked Synchronous Transmission by DTC
468
Figure 13.27 Sample Flowchart for Mode Transition During Transmission
469
Figure 13.28 Port Pin State of Asynchronous Transmission Using Internal Clock
470
Figure 13.29 Port Pin State of Synchronous Transmission Using Internal Clock
470
Switching from SCK Pin Function to Port Pin Function
471
Figure 13.30 Sample Flowchart for Mode Transition During Reception
471
Figure 13.31 Operation When Switching from SCK Pin Function to Port Pin Function
472
Figure 13.32 Operation When Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output)
473
Section 14 Boundary Scan Function
475
Features
475
Section 14 Boundary Scan Function
476
Figure 14.1 Block Diagram of Boundary Scan Function
476
Section 14 Boundary Scan Function
477
Pin Configuration
477
Table 14.1 Pin Configuration
477
Register Descriptions
478
Instruction Register (INSTR)
478
Table 14.2 Instruction Configuration
478
IDCODE Register (IDCODE)
480
BYPASS Register (BYPASS)
480
Boundary Scan Register (BSCANR)
480
Table 14.3 IDCODE Register Configuration
480
Figure 14.2 Boundary Scan Register Configuration
481
Table 14.4 Correspondence between LSI Pins and Boundary Scan Register
482
Boundary Scan Function Operation
489
TAP Controller
489
Usage Notes
489
Figure 14.3 TAP Controller Status Transition
489
Figure 14.4 Recommended Reset Signal Design
490
Figure 14.5 Serial Data Input/Output
490
Section 15 Universal Serial Bus Interface (USB)
491
Features
491
Section 15 Universal Serial Bus Interface (USB)
493
Figure 15.1 Block Diagram of USB
493
Section 15 Universal Serial Bus Interface (USB)
494
Input/Output Pins
494
Table 15.1 Pin Configuration
494
Register Descriptions
495
USB Endpoint Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)
496
UEPIR00_0 to UEPIR22
496
Figure 15.2 Example of Endpoint Configuration Based on Bluetooth Standard
500
Table 15.2 EPINFO Data Settings
501
USB Control Register (UCTLR)
503
USB DMAC Transfer Request Register (UDMAR)
507
USB Device Resume Register (UDRR)
508
USB Trigger Register 0 (UTRG0)
509
USB Trigger Register 1 (UTRG1)
510
USBFIFO Clear Register 0 (UFCLR0)
511
USBFIFO Clear Register 1 (UFCLR1)
512
USB Endpoint Stall Register 0 (UESTL0)
513
USB Endpoint Stall Register 1 (UESTL1)
514
USB Endpoint Data Register 0S (Uedr0S)
515
USB Endpoint Data Register 0I (Uedr0I)
515
USB Endpoint Data Register 0O (Uedr0O)
515
USB Endpoint Data Register 1I (Uedr1I)
516
USB Endpoint Data Register 2I (Uedr2I)
516
USB Endpoint Data Register 2O (Uedr2O)
516
USB Endpoint Data Register 3I (Uedr3I)
517
USB Endpoint Data Register 3O (Uedr3O)
517
USB Endpoint Data Register 4I (Uedr4I)
517
USB Endpoint Data Register 4O (Uedr4O)
518
USB Endpoint Data Register 5I (Uedr5I)
518
USB Endpoint Receive Data Size Register 0O (Uesz0O)
518
USB Endpoint Receive Data Size Register 2O (Uesz2O)
519
USB Endpoint Receive Data Size Register 3O (Uesz3O)
519
USB Endpoint Receive Data Size Register 4O (Uesz4O)
519
USB Interrupt Flag Register 0 (UIFR0)
519
USB Interrupt Flag Register 1 (UIFR1)
522
USB Interrupt Flag Register 2 (UIFR2)
524
USB Interrupt Flag Register 3 (UIFR3)
526
USB Interrupt Enable Register 0 (UIER0)
528
USB Interrupt Enable Register 1 (UIER1)
528
USB Interrupt Enable Register 2 (UIER2)
529
USB Interrupt Enable Register 3 (UIER3)
529
USB Interrupt Select Register 0 (UISR0)
530
USB Interrupt Select Register 1 (UISR1)
530
USB Interrupt Select Register 2 (UISR2)
531
USB Interrupt Select Register 3 (UISR3)
531
USB Data Status Register (UDSR)
532
USB Configuration Value Register (UCVR)
533
USB Time Stamp Registers H, L (UTSRH, UTSRL)
534
USB Test Register 0 (UTSTR0)
535
Table 15.3 Relationship between the UTSTR0 Setting and Pin Outputs
536
USB Test Register 1 (UTSTR1)
537
USB Test Registers 2 and a to F (UTSTR2, UTSRA to UTSRF)
538
Table 15.4 Relationship between the UTSTR1 Settings and Pin Inputs
538
Module Stop Control Register B (MSTPCRB)
539
Interrupt Sources
540
Table 15.5 SCI Interrupt Sources
540
Communication Operation
542
Initialization
542
Figure 15.3 USB Initialization
542
USB Cable Connection/Disconnection
543
Figure 15.4 USB Cable Connection (When USB Module Stop or Software Standby Is Not Used)
543
Figure 15.5 USB Cable Connection (When USB Module Stop or Software Standby Is Used)
544
Figure 15.6 USB Cable Disconnection (When USB Module Stop or Software Standby Is Not Used)
545
Figure 15.7 USB Cable Disconnection (When USB Module Stop or Software Standby Is Used)
546
Suspend and Resume Operations
547
Figure 15.8 Suspend Operation
547
Figure 15.9 Resume Operation from Up-Stream
548
Figure 15.10 Operation When Remote-Wakeup Function Is Used
549
Control Transfer
550
Figure 15.11 Control Transfer Stage Configuration
550
Figure 15.12 Setup Stage Operation
551
Figure 15.13 Data Stage Operation (Control-In)
553
Figure 15.14 Data Stage Operation (Control-Out)
554
Figure 15.15 Status Stage Operation (Control-In)
555
Figure 15.16 Status Stage Operation (Control-Out)
556
Interrupt-In Transfer: (Ep1I Is Specified as Endpoint)
557
Figure 15.17 Ep1I Interrupt-In Transfer Operation
557
Bulk-In Transfer (Dual Fifos): (Ep2I Is Specified as Endpoint)
558
Figure 15.18 Ep2I Bulk-In Transfer Operation
559
Bulk-Out Transfer (Dual Fifos): (Ep2O Is Specified as Endpoint)
560
Figure 15.19 Ep2O Bulk-In Transfer Operation
561
Isochronous-In Transfer (Dual-FIFO) (When Ep3I Is Specified as Endpoint)
562
Figure 15.20 Ep3I Isochronous-In Transfer Operation
563
Isochronous-Out Transfer (Dual-FIFO) (When Ep3O Is Specified as Endpoint)
564
Figure 15.21 Ep3O Isochronous-Out Transfer Operation
565
15.5.10 Processing of USB Standard Commands and Class/Vendor Commands
566
15.5.11 Stall Operations
566
Table 15.6 Command Decoding on Firmware
566
Figure 15.22 Forcible Stall by Firmware
568
Figure 15.23 Automatic Stall by USB Function Module
570
DMA Transfer Specifications
571
Overview
571
On-Chip DMAC Settings
571
Ep2I and Ep4I DMA Transfer
571
Ep2O and Ep4O DMA Transfer
571
Ep2Ipkte, Ep4Ipkte, Ep2Ordfn and Ep4Ordfn Bits of UTRG
572
Figure 15.24 Ep2Ipkte Operation in UTRG0
572
Figure 15.25 Ep2Ordfn Operation in UTRG0
573
Endpoint Configuration Example
574
Figure 15.26 Endpoint Configuration Example
574
Table 15.7 Register Name Modification List
575
Table 15.8 Bit Name Modification List
576
Table 15.9 EPINFO Data Settings
577
USB External Circuit Example
579
Figure 15.27 USB External Circuit in Bus-Powered Mode (When On-Chip Transceiver Is Used)
579
Figure 15.28 USB External Circuit in Self-Powered Mode (When On-Chip Transceiver Is Used)
580
Figure 15.29 USB External Circuit in Bus-Powered Mode (When External Transceiver Is Used)
581
Figure 15.30 USB External Circuit in Self-Powered Mode (When External Transceiver Is Used)
582
Usage Notes
583
Operating Frequency
583
Bus Interface
583
Setup Data Reception
583
FIFO Clear
583
IRQ6 Interrupt
583
Data Register Overread or Overwrite
584
Ep3O Isochronous Transfer
585
Figure 15.31 10-Byte Data Reception
585
Figure 15.32 Ep3O Data Reception
586
Reset
587
EP0 Interrupt Assignment
587
Level Shifter for VBUS and Irqx Pins
587
15.9.11 USB Endpoint Data Read and Write
587
15.9.12 Restrictions for Software Standby Mode Transition
588
Figure 15.33 Transition to and from Software Standby Mode
589
15.9.13 USB External Circuit Example
590
Figure 15.34 USB Software Standby Mode Transition Timing
590
Section 16 A/D Converter
591
Features
591
Section 16 A/D Converter
592
Figure 16.1 Block Diagram of A/D Converter
592
Section 16 A/D Converter
593
Input/Output Pins
593
Register Descriptions
593
A/D Data Registers a to D (ADDRA to ADDRD)
593
Table 16.1 Pin Configuration
593
A/D Control/Status Register (ADCSR)
594
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
594
A/D Control Register (ADCR)
596
Interface to Bus Master
597
Figure 16.2 Access to ADDR (When Reading H'AA40)
597
Operation
598
Single Mode
598
Scan Mode
599
Figure 16.3 A/D Conversion Timing (Single-Chip Mode, Channel 1 Selected)
599
Input Sampling and A/D Conversion Time
600
Figure 16.4 A/D Conversion Timing (Scan Mode, Channels AN0 to AN3 Selected)
600
Figure 16.5 A/D Conversion Timing
601
Table 16.3 A/D Conversion Time (Single Mode)
601
Table 16.4 A/D Conversion Time (Scan Mode)
601
External Trigger Input Timing
602
Interrupts
602
Figure 16.6 External Trigger Input Timing
602
Table 16.5 A/D Converter Interrupt Source
602
A/D Conversion Precision Definitions
603
Figure 16.7 A/D Conversion Precision Definitions (1)
604
Figure 16.8 A/D Conversion Precision Definitions (2)
604
Usage Notes
605
Permissible Signal Source Impedance
605
Influences on Absolute Precision
605
Range of Analog Power Supply and Other Pin Settings
605
Figure 16.9 Example of Analog Input Circuit
605
Notes on Board Design
606
Notes on Noise Countermeasures
606
Figure 16.10 Example of Analog Input Protection Circuit
607
Figure 16.11 Analog Input Pin Equivalent Circuit
607
Table 16.6 Analog Pin Specifications
607
Section 17 D/A Converter
609
Section 17 D/A Converter
609
Features
609
Figure 17.1 Block Diagram of D/A Converter
609
Section 17 D/A Converter
610
Input/Output Pins
610
Register Description
610
D/A Data Register (DADR)
610
Table 17.1 Pin Configuration
610
D/A Control Register (DACR)
611
Operation
611
Figure 17.2 Example of D/A Converter Operation
612
Section 18 RAM
613
Section 19 Flash Memory (F-ZTAT Version)
615
Features
615
Section 19 Flash Memory (F-ZTAT Version)
616
Figure 19.1 Block Diagram of Flash Memory
616
Mode Transitions
617
Figure 19.2 Flash Memory State Transitions
617
Section 19 Flash Memory (F-ZTAT Version)
618
Table 19.1 Differences between Boot Mode and User Program Mode
618
Figure 19.3 Boot Mode
619
Figure 19.4 User Program Mode
620
Block Configuration
621
Figure 19.5 Flash Memory Block Configuration
621
Input/Output Pins
622
Register Descriptions
622
Table 19.2 Pin Configuration
622
Flash Memory Control Register 1 (FLMCR1)
623
Flash Memory Control Register 2 (FLMCR2)
624
Erase Block Register 1 (EBR1)
625
Erase Block Register 2 (EBR2)
626
RAM Emulation Register (RAMER)
627
Serial Control Register X (SCRX)
628
On-Board Programming Modes
629
SCI Boot Mode(HD64F2215)
629
Table 19.3 Setting On-Board Programming Modes
629
Figure 19.6 SCI System Configuration in Boot Mode
630
Table 19.4 SCI Boot Mode Operation
632
Table 19.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is Possible
632
USB Boot Mode (HD64F2215U)
633
Table 19.6 Enumeration Information
633
Figure 19.7 System Configuration Diagram When Using USB Boot Mode
634
Table 19.7 USB Boot Mode Operation
636
Figure 19.8 Programming/Erasing Flowchart Example in User Program Mode
638
Programming/Erasing in User Program Mode
639
Figure 19.9 Flowchart for Flash Memory Emulation in RAM
639
Flash Memory Emulation in RAM
640
Figure 19.10 Example of RAM Overlap Operation
640
Flash Memory Programming/Erasing
641
Program/Program-Verify
641
Figure 19.11 Program/Program-Verify Flowchart
642
Erase/Erase-Verify
643
Figure 19.12 Erase/Erase-Verify Flowchart
644
Program/Erase Protection
645
Hardware Protection
645
Software Protection
645
Error Protection
645
Interrupt Handling When Programming/Erasing Flash Memory
646
Programmer Mode
646
Figure 19.13 Memory Map in Programmer Mode
646
Power-Down States for Flash Memory
647
Flash Memory Programming and Erasing Precautions
647
Table 19.8 Flash Memory Operating States
647
Note on Switching from F-ZTAT Version to Masked ROM Version
649
Table 19.9 Registers Present in F-ZTAT Version but Absent in Masked ROM Version
649
Section 20 Masked ROM
651
Section 20 Masked ROM
651
Features
651
Figure 20.1 Block Diagram of On-Chip Masked ROM (256 Kbytes)
651
Section 21 Clock Pulse Generator
653
Section 21 Clock Pulse Generator
653
Figure 21.1 Block Diagram of Clock Pulse Generator
653
Register Descriptions
654
System Clock Control Register (SCKCR)
654
Low-Power Control Register (LPWRCR)
656
Section 21 Clock Pulse Generator
657
System Clock Oscillator
657
Connecting a Crystal Resonator
657
Figure 21.2 Connection of Crystal Resonator (Example)
657
Figure 21.3 Crystal Resonator Equivalent Circuit
657
Table 21.1 Damping Resistance Value
657
Table 21.2 Crystal Resonator Characteristics
657
Inputting an External Clock
658
Figure 21.4 External Clock Input (Examples)
658
Table 21.3 External Clock Input Conditions
658
Duty Adjustment Circuit
659
Medium-Speed Clock Divider
659
Bus Master Clock Selection Circuit
659
Figure 21.5 External Clock Input Timing
659
Table 21.4 External Clock Input Conditions When Duty Adjustment Circuit Is Not Used
659
USB Operating Clock
660
Connecting a Ceramic Resonator
660
Inputting an 48-Mhz External Clock
660
Figure 21.6 Connection of Ceramic Resonator
660
Figure 21.7 Connection of Ceramic Resonator
660
Pin Handling When 48-Mhz External Clock Is Not Needed
661
(On-Chip PLL Circuit Is Used)
661
PLL Circuit for USB
661
Figure 21.8 48-Mhz External Clock Input Timing
661
Figure 21.9 Pin Handling When 48-Mhz External Clock Is Not Used
661
Table 21.5 External Clock Input Conditions When Duty Adjustment Circuit Is Not Used
661
Usage Notes
662
Note on Crystal Resonator
662
Note on Board Design
662
Figure 21.10 Example of PLL Circuit
662
Note on Switchover of External Clock
663
Figure 21.11 Note on Board Design of Oscillator Circuit
663
Figure 21.12 Example of External Clock Switching Circuit
663
Figure 21.13 Example of External Clock Switchover Timing
664
Section 22 Power-Down Modes
665
Section 22 Power-Down Modes
666
Table 22.1 LSI Internal States in each Mode
666
Section 22 Power-Down Modes
667
Figure 22.1 Mode Transition Diagram
667
Table 22.2 Low Power Dissipation Mode Transition Conditions
667
Register Descriptions
668
Standby Control Register (SBYCR)
668
System Clock Control Register (SCKCR)
670
Module Stop Control Registers a to C (MSTPCRA to MSTPCRC)
670
Medium-Speed Mode
672
Figure 22.2 Medium-Speed Mode Transition and Clearance Timing
672
Sleep Mode
673
Transition to Sleep Mode
673
Exiting Sleep Mode
673
Software Standby Mode
673
Transition to Software Standby Mode
673
Clearing Software Standby Mode
674
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
674
Software Standby Mode Application Example
675
Table 22.3 Oscillation Stabilization Time Settings
675
Hardware Standby Mode
676
Transition to Hardware Standby Mode
676
Clearing Hardware Standby Mode
676
Figure 22.3 Software Standby Mode Application Example
676
Hardware Standby Mode Timing
677
Hardware Standby Mode Timings
677
Figure 22.4 Hardware Standby Mode Timing (Example)
677
Figure 22.5 Timing of Transition to Hardware Standby Mode
677
Module Stop Mode
678
Clock Output Disabling Function
678
Figure 22.6 Timing of Recovery from Hardware Standby Mode
678
Usage Notes
679
I/O Port Status
679
Current Dissipation During Oscillation Stabilization Wait Period
679
DMAC and DTC Module Stop
679
On-Chip Supporting Module Interrupt
679
Table 22.4 Ø Pin State in each Processing State
679
Section 23 List of Registers
681
Register Addresses (Address Order)
681
Register Bits
690
Register States in each Operating Mode
700
Section 24 Electrical Characteristics
707
Section 24 Electrical Characteristics
707
Absolute Maximum Ratings
707
Table 24.1 Absolute Maximum Ratings
707
Section 24 Electrical Characteristics
708
Power Supply Voltage and Operating Frequency Range
708
Figure 24.1 Power Supply Voltage and Operating Ranges
708
DC Characteristics
709
Table 24.2 DC Characteristics
709
AC Characteristics
712
Figure 24.2 Output Load Circuit
712
Table 24.3 Permissible Output Currents
712
Clock Timing
713
Figure 24.3 System Clock Timing
713
Table 24.4 Clock Timing
713
Control Signal Timing
714
Figure 24.4 Oscillation Stabilization Timing
714
Table 24.5 Control Signal Timing
714
Figure 24.5 Reset Input Timing
715
Figure 24.6 Interrupt Input Timing
715
Bus Timing
716
Table 24.6 Bus Timing
716
Figure 24.7 Basic Bus Timing (Two-State Access)
717
Figure 24.8 Basic Bus Timing (Three-State Access)
718
Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State)
719
Figure 24.10 Burst ROM Access Timing (Two-State Access)
720
Figure 24.11 External Bus Release Timing
721
Table 24.7 Timing of On-Chip Supporting Modules
722
Timing of On-Chip Supporting Modules
722
Figure 24.12 I/O Port Input/Output Timing
724
Figure 24.13 TPU Input/Output Timing
724
Figure 24.14 TPU Clock Input Timing
724
Figure 24.15 8-Bit Timer Output Timing
725
Figure 24.16 8-Bit Timer Clock Input Timing
725
Figure 24.17 8-Bit Timer Reset Input Timing
725
Figure 24.18 SCK Clock Input Timing
725
Figure 24.19 SCI Input/Output Timing (Clock Synchronous Mode)
726
Figure 24.20 A/D Converter External Trigger Input Timing
726
Figure 24.21 Boundary Scan TCK Input Timing
726
Figure 24.22 Boundary Scan TRST Input Timing (at Reset Hold)
726
Figure 24.23 Boundary Scan Data Transmission Timing
727
UBS Characteristics
728
Figure 24.24 Data Signal Timing
728
Table 24.8 USB Characteristics (USD+ and USD- Pins) When On-Chip USB Transceiver Is Used
728
A/D Conversion Characteristics
729
Figure 24.25 Test Load Circuit
729
Table 24.9 A/D Conversion Characteristics
729
D/A Conversion Characteristics
730
Flash Memory Characteristics
730
Table 24.10 D/A Conversion Characteristics
730
Table 24.11 Flash Memory Characteristics
730
Usage Note
731
Appendix
733
I/O Port States in each Processing State
733
Product Model Lineup
737
Appendix
738
Package Dimensions
738
Figure C.1 TFP-120 Package Dimension
738
Figure C.2 BP-112 Package Dimension
739
Index
741
Section 12 Watchdog Timer
744
Section 13 Serial Communication Interface
744
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