Address Error Exception Processing; Interrupts; Interrupt Sources - Hitachi SH7095 Hardware User Manual

4.3.2

Address Error Exception Processing

When an address error occurs, the bus cycle in which the error occurred ends. When the executing
instruction finishes, address error exception processing begins. The CPU operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the address error that occurred and the program starts executing from
that address. The jump that occurs is not a delay branch.
4.4

Interrupts

4.4.1

Interrupt Sources

Table 4.7 shows the sources that start up interrupt exception processing. These are divided into
NMI, user breaks, IRL, and on-chip peripheral modules. Each interrupt source is allocated a
different vector number and vector table address offset. See section 5, Interrupt Controller for
more information.
Table 4.7 Types of Interrupt Sources
Type
NMI
User break
IRL
On-chip peripheral module
60 Hitachi
Request Source
NMI pin (external input)
User break controller
IRL0–IRL15 (external input)
Direct memory access controller (DMAC)
Division
Serial communications interface (SCI)
A/D converter
Free running timer
Watchdog timer (WDT)
Bus state controller (BSC)
Number of Sources
1
1
15
2
1
4
1
3
1
1