Hitachi H8/3022 F-ZTAT Manuals

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Hitachi H8/3022 F-ZTAT Hardware Manual

Hitachi H8/3022 F-ZTAT Hardware Manual (674 pages)

H8/3022 Series Hitachi Single-Chip Microcomputer  
Brand: Hitachi | Category: Computer Hardware | Size: 2.08 MB
Table of contents
Table Of Contents4................................................................................................................................................................
Section 1 Overview15................................................................................................................................................................
Overview15................................................................................................................................................................
Block Diagram19................................................................................................................................................................
Pin Description20................................................................................................................................................................
Pin Arrangement20................................................................................................................................................................
Pin Functions21................................................................................................................................................................
Cpu29................................................................................................................................................................
Features29................................................................................................................................................................
Differences From H8/300 Cpu30................................................................................................................................................................
Cpu Operating Modes31................................................................................................................................................................
Address Space32................................................................................................................................................................
Register Configuration33................................................................................................................................................................
General Registers34................................................................................................................................................................
Control Registers35................................................................................................................................................................
Initial Cpu Register Values36................................................................................................................................................................
Data Formats37................................................................................................................................................................
General Register Data Formats37................................................................................................................................................................
Memory Data Formats38................................................................................................................................................................
Instruction Set40................................................................................................................................................................
Instruction Set Overview40................................................................................................................................................................
Instructions And Addressing Modes41................................................................................................................................................................
Tables Of Instructions Classified By Function43................................................................................................................................................................
Basic Instruction Formats53................................................................................................................................................................
Notes On Use Of Bit Manipulation Instructions54................................................................................................................................................................
Addressing Modes And Effective Address Calculation55................................................................................................................................................................
Addressing Modes55................................................................................................................................................................
Effective Address Calculation57................................................................................................................................................................
Processing States61................................................................................................................................................................
Program Execution State62................................................................................................................................................................
Exception-handling State62................................................................................................................................................................
Exception-handling Sequences64................................................................................................................................................................
Reset State65................................................................................................................................................................
Power-down State65................................................................................................................................................................
Basic Operational Timing66................................................................................................................................................................
On-chip Memory Access Timing66................................................................................................................................................................
On-chip Supporting Module Access Timing67................................................................................................................................................................
Access To External Address Space68................................................................................................................................................................
Mcu Operating Modes69................................................................................................................................................................
Operating Mode Selection69................................................................................................................................................................
Mode Control Register (mdcr)71................................................................................................................................................................
System Control Register (syscr)72................................................................................................................................................................
Operating Mode Descriptions74................................................................................................................................................................
Mode 174................................................................................................................................................................
Mode 374................................................................................................................................................................
Pin Functions In Each Operating Mode75................................................................................................................................................................
Memory Map In Each Operating Mode75................................................................................................................................................................
Exception Handling82................................................................................................................................................................
Exception Handling Types And Priority82................................................................................................................................................................
Exception Handling Operation82................................................................................................................................................................
Exception Vector Table83................................................................................................................................................................
Reset85................................................................................................................................................................
Reset Sequence85................................................................................................................................................................
Interrupts After Reset87................................................................................................................................................................
Interrupts87................................................................................................................................................................
Trap Instruction88................................................................................................................................................................
Stack Status After Exception Handling88................................................................................................................................................................
Notes On Stack Usage89................................................................................................................................................................
Interrupt Controller90................................................................................................................................................................
Pin Configuration92................................................................................................................................................................
Register Descriptions93................................................................................................................................................................
Interrupt Priority Registers A And B (ipra, Iprb)95................................................................................................................................................................
Irq Status Register (isr)100................................................................................................................................................................
Irq Enable Register (ier)101................................................................................................................................................................
Irq Sense Control Register (iscr)102................................................................................................................................................................
Interrupt Sources103................................................................................................................................................................
External Interrupts103................................................................................................................................................................
Internal Interrupts104................................................................................................................................................................
Interrupt Vector Table104................................................................................................................................................................
Interrupt Operation107................................................................................................................................................................
Interrupt Handling Process107................................................................................................................................................................
Interrupt Sequence112................................................................................................................................................................
Interrupt Response Time113................................................................................................................................................................
Usage Notes114................................................................................................................................................................
Contention Between Interrupt And Interrupt-disabling Instruction114................................................................................................................................................................
Instructions That Inhibit Interrupts115................................................................................................................................................................
Interrupts During Eepmov Instruction Execution115................................................................................................................................................................
Bus Controller118................................................................................................................................................................
Access State Control Register (astcr)121................................................................................................................................................................
Wait Control Register (wcr)122................................................................................................................................................................
Wait State Controller Enable Register (wcer)123................................................................................................................................................................
Address Control Register (adrcr)124................................................................................................................................................................
Operation126................................................................................................................................................................
Area Division126................................................................................................................................................................
Memory Map126................................................................................................................................................................
Bus Control Signal Timing128................................................................................................................................................................
Wait Modes130................................................................................................................................................................
Interconnections With Memory (example)136................................................................................................................................................................
Register Write Timing138................................................................................................................................................................
Precautions On Setting Astcr And Abwcr138................................................................................................................................................................
I/o Ports139................................................................................................................................................................
Port 1143................................................................................................................................................................
Pin Functions In Each Mode150................................................................................................................................................................
Port 2164................................................................................................................................................................
Port B185................................................................................................................................................................
16-bit Integrated Timer Unit (itu)193................................................................................................................................................................
Block Diagrams196................................................................................................................................................................
Timer Start Register (tstr)203................................................................................................................................................................
Timer Synchro Register (tsnc)207................................................................................................................................................................
Timer Mode Register (tmdr)209................................................................................................................................................................
Timer Function Control Register (tfcr)212................................................................................................................................................................
Timer Output Master Enable Register (toer)214................................................................................................................................................................
Timer Output Control Register (tocr)217................................................................................................................................................................
Timer Counters (tcnt)218................................................................................................................................................................
General Registers (gra, Grb)219................................................................................................................................................................
Buffer Registers (bra, Brb)220................................................................................................................................................................
Timer Control Registers (tcr)221................................................................................................................................................................
Timer I/o Control Register (tior)224................................................................................................................................................................
Timer Status Register (tsr)226................................................................................................................................................................
Timer Interrupt Enable Register (tier)228................................................................................................................................................................
Cpu Interface230................................................................................................................................................................
16-bit Accessible Registers230................................................................................................................................................................
8-bit Accessible Registers232................................................................................................................................................................
Basic Functions234................................................................................................................................................................
Synchronization244................................................................................................................................................................
Pwm Mode246................................................................................................................................................................
Reset-synchronized Pwm Mode250................................................................................................................................................................
Complementary Pwm Mode253................................................................................................................................................................
Phase Counting Mode263................................................................................................................................................................
Buffering265................................................................................................................................................................
Itu Output Timing272................................................................................................................................................................
Setting Of Status Flags274................................................................................................................................................................
Clearing Of Status Flags276................................................................................................................................................................
Programmable Timing Pattern Controller293................................................................................................................................................................
Port A Data Direction Register (paddr)297................................................................................................................................................................
Port A Data Register (padr)297................................................................................................................................................................
Port B Data Direction Register (pbddr)298................................................................................................................................................................
Port B Data Register (pbdr)298................................................................................................................................................................
Next Data Register A (ndra)299................................................................................................................................................................
Next Data Register B (ndrb)301................................................................................................................................................................
Next Data Enable Register A (ndera)303................................................................................................................................................................
Next Data Enable Register B (nderb)304................................................................................................................................................................
Tpc Output Control Register (tpcr)305................................................................................................................................................................
Tpc Output Mode Register (tpmr)308................................................................................................................................................................
Output Timing311................................................................................................................................................................
Normal Tpc Output313................................................................................................................................................................
Non-overlapping Tpc Output314................................................................................................................................................................
Operation Of Tpc Output Pins317................................................................................................................................................................
Note On Non-overlapping Output317................................................................................................................................................................
Section 10 Watchdog Timer319................................................................................................................................................................
Timer Counter (tcnt)321................................................................................................................................................................
Timer Control/status Register (tcsr)323................................................................................................................................................................
Reset Control/status Register (rstcsr)325................................................................................................................................................................
Notes On Register Access327................................................................................................................................................................
Watchdog Timer Operation330................................................................................................................................................................
Interval Timer Operation330................................................................................................................................................................
Timing Of Setting Of Overflow Flag (ovf)331................................................................................................................................................................
Timing Of Setting Of Watchdog Timer Reset Bit (wrst)332................................................................................................................................................................
Section 11 Serial Communication Interface334................................................................................................................................................................
Receive Shift Register (rsr)338................................................................................................................................................................
Receive Data Register (rdr)338................................................................................................................................................................
Transmit Shift Register (tsr)339................................................................................................................................................................
Transmit Data Register (tdr)339................................................................................................................................................................
Serial Mode Register (smr)340................................................................................................................................................................
Serial Control Register (scr)344................................................................................................................................................................
Serial Status Register (ssr)348................................................................................................................................................................
Bit Rate Register (brr)352................................................................................................................................................................
Operation In Asynchronous Mode363................................................................................................................................................................
Multiprocessor Communication372................................................................................................................................................................
Synchronous Operation379................................................................................................................................................................
Sci Interrupts388................................................................................................................................................................
Section 12 Smart Card Interface394................................................................................................................................................................
Smart Card Mode Register (scmr)397................................................................................................................................................................
Pin Connections401................................................................................................................................................................
Data Format403................................................................................................................................................................
Register Settings405................................................................................................................................................................
Clock407................................................................................................................................................................
Data Transfer Operations409................................................................................................................................................................
Usage Note415................................................................................................................................................................
Section 13 A/d Converter418................................................................................................................................................................
A/d Data Registers A To D (addra To Addrd)422................................................................................................................................................................
A/d Control/status Register (adcsr)423................................................................................................................................................................
A/d Control Register (adcr)426................................................................................................................................................................
Single Mode (scan = 0)428................................................................................................................................................................
Scan Mode (scan = 1)430................................................................................................................................................................
Input Sampling And A/d Conversion Time432................................................................................................................................................................
External Trigger Input Timing433................................................................................................................................................................
Section 14 Ram440................................................................................................................................................................
Section 15 Rom444................................................................................................................................................................
Mode Transitions446................................................................................................................................................................
On-board Programming Modes447................................................................................................................................................................
Flash Memory Emulation In Ram449................................................................................................................................................................
Differences Between Boot Mode And User Program Mode450................................................................................................................................................................
Block Configuration451................................................................................................................................................................
Flash Memory Control Register 1 (flmcr1)452................................................................................................................................................................
Flash Memory Control Register 2 (flmcr2)455................................................................................................................................................................
Erase Block Register 1 (ebr1)456................................................................................................................................................................
Erase Block Register 2 (ebr2)457................................................................................................................................................................
Ram Emulation Register (ramer)458................................................................................................................................................................
Differences From H8/3039 F-ztat Series460................................................................................................................................................................
Boot Mode462................................................................................................................................................................
User Program Mode468................................................................................................................................................................
Programming/erasing Flash Memory469................................................................................................................................................................
Program Mode470................................................................................................................................................................
Program-verify Mode471................................................................................................................................................................
Notes On Program/program-verify Procedure471................................................................................................................................................................
Erase Mode476................................................................................................................................................................
Erase-verify Mode476................................................................................................................................................................
Protection478................................................................................................................................................................
Hardware Protection478................................................................................................................................................................
Software Protection479................................................................................................................................................................
Error Protection480................................................................................................................................................................
Nmi Input Disable Conditions482................................................................................................................................................................
Flash Memory Prom Mode485................................................................................................................................................................
Socket Adapters And Memory Map485................................................................................................................................................................
Notes On Use Of Prom Mode486................................................................................................................................................................
Notes On Flash Memory Programming/erasing487................................................................................................................................................................
Overview Of Mask Rom493................................................................................................................................................................
Notes On Ordering Mask Rom Version Chips494................................................................................................................................................................
Notes When Converting The F-ztat Application Software To The Mask-rom Versions495................................................................................................................................................................
Section 16 Clock Pulse Generator496................................................................................................................................................................
Oscillator Circuit498................................................................................................................................................................
Connecting A Crystal Resonator498................................................................................................................................................................
External Clock Input500................................................................................................................................................................
Duty Adjustment Circuit503................................................................................................................................................................
Prescalers503................................................................................................................................................................
Frequency Divider503................................................................................................................................................................
Division Control Register (divcr)504................................................................................................................................................................
Section 17 Power-down State505................................................................................................................................................................
Module Standby Control Register (mstcr)509................................................................................................................................................................
Sleep Mode511................................................................................................................................................................
Transition To Sleep Mode511................................................................................................................................................................
Exit From Sleep Mode511................................................................................................................................................................
Software Standby Mode512................................................................................................................................................................
Transition To Software Standby Mode512................................................................................................................................................................
Exit From Software Standby Mode512................................................................................................................................................................
Selection Of Oscillator Waiting Time After Exit From Software Standby Mode513................................................................................................................................................................
Sample Application Of Software Standby Mode514................................................................................................................................................................
Transition To Hardware Standby Mode515................................................................................................................................................................
Exit From Hardware Standby Mode515................................................................................................................................................................
Timing For Hardware Standby Mode515................................................................................................................................................................
Module Standby Function516................................................................................................................................................................
Module Standby Timing516................................................................................................................................................................
Read/write In Module Standby516................................................................................................................................................................
System Clock Output Disabling Function517................................................................................................................................................................
Section 18 Electrical Characteristics518................................................................................................................................................................
Electrical Characteristics Of Masked Rom Version518................................................................................................................................................................
Absolute Maximum Ratings518................................................................................................................................................................
Dc Characteristics519................................................................................................................................................................
Ac Characteristics523................................................................................................................................................................
A/d Conversion Characteristics528................................................................................................................................................................
Electrical Characteristics Of Flash Memory Version529................................................................................................................................................................
Flash Memory Characteristics540................................................................................................................................................................
Operational Timing541................................................................................................................................................................
Bus Timing541................................................................................................................................................................
Control Signal Timing545................................................................................................................................................................
Clock Timing547................................................................................................................................................................
Tpc And I/o Port Timing547................................................................................................................................................................
Itu Timing548................................................................................................................................................................
Sci Input/output Timing549................................................................................................................................................................
Appendix A Instruction Set550................................................................................................................................................................
Instruction List550................................................................................................................................................................
Data Transfer Instructions552................................................................................................................................................................
Arithmetic Instructions554................................................................................................................................................................
Bit Manipulation Instructions559................................................................................................................................................................
Number Of States Required For Execution568................................................................................................................................................................
Appendix B Internal I/o Register Field578................................................................................................................................................................
Addresses578................................................................................................................................................................
Function585................................................................................................................................................................
Appendix C I/o Block Diagrams644................................................................................................................................................................
Port 1 Block Diagram644................................................................................................................................................................
Port 2 Block Diagram645................................................................................................................................................................
Port 3 Block Diagram646................................................................................................................................................................
Port 5 Block Diagram647................................................................................................................................................................
Port 6 Block Diagrams648................................................................................................................................................................
Port 7 Block Diagram650................................................................................................................................................................
Port 8 Block Diagrams651................................................................................................................................................................
Port 9 Block Diagrams653................................................................................................................................................................
Port A Block Diagrams657................................................................................................................................................................
Port B Block Diagrams660................................................................................................................................................................
Appendix D Pin States663................................................................................................................................................................
Port States In Each Mode663................................................................................................................................................................
Pin States At Reset665................................................................................................................................................................
Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode668................................................................................................................................................................
Appendix F Product Code Lineup669................................................................................................................................................................
Appendix G Package Dimensions670................................................................................................................................................................
Appendix H Comparison Of H8/300h Series Product Specifications672................................................................................................................................................................
Differences Between H8/3039f And H8/3022f672................................................................................................................................................................

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