Fujitsu MB96300 series Hardware Manual page 59

MB96300 Super Series Hardware Manual
• Write back (WB): Writes the operation result to a register or memory location.
CLK
Instruction 1 WB
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead of instruction
B, instruction A always reaches write back stage before instruction B.
The standard instruction execution speed is one instruction per cycle. However, transfer instructions that
involve memory wait, branch instructions and multi-cycle instructions require more than one cycle to
execute. The instruction execution speed also drops if the delivery of instructions during code fetch is slow.
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Instruction Queue
The CPU has an instruction queue of 8 byte.
The instruction queue is filled by the fetch unit. Prefetch is used on consecutive addresses for code fetch. The
prefetch mechanism removes drawbacks due to the latency of the pipelined implementation of the CPU and
the system bus of the 16FX core.
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Program counter
The program counter bank (PCB, upper 8 bits of the program address) and the program counter (PC, lower
16 bits of the program address) are controlled by the decode stage 1.
The 24-bit address of the concatenation of {PCB, PC} points to the instruction, which is executed next.
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ALU
The ALU is controlled by decode stage 2. The operation mode of the ALU is selected and the operands are
loaded. The execution of the operation is performed in the next cycle.
The ALU is used for logical and arithmetical operations. Multiplication and division are included.
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CPU registers and memory access
In the write back stage the result of the operation is written to CPU registers and/or to a memory location. All
CPU registers except the program counter are assigned to the last pipeline stage.
■ Hardware structure of the 16FX Core
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Block Diagram
A sample configuration and the principle structure of a MCU device based on the 16FX Core is shown in
Figure 2.2-3 "MCU Device based on the 16FX Core".
Figure 2.2-2 Instruction Pipeline
EX WB
D2 EX
D1 D2
IF D1
IF
WB
EX WB
D2 EX
D1 D2
CHAPTER 2 CPU
WB
EX WB
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