Transfer Type; 2-Cycle Transfer; Fly-By Transfer; Dma Transfer And Interrupts - Fujitsu FR Series Application Note

DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access

2.4.2 Transfer Type

2.4.2.1 2-cycle Transfer

In 2-cycle transfer the DMAC performs 2 operations sequentially. Upon receiving the
transfer request it reads the data from an address specified in the transfer source register
DMASA and then writes it to the address as specified by transfer destination register DMADA.
In case of block/step 2-cycle transfer all areas accessible by 32-bit addressing are
specifiable, however for demand 2-cycle transfer make sure to set an external area address
as transfer source or transfer destination or both.

2.4.2.2 Fly-by Transfer

Fly-by transfer is used when the data needs to be transferred from one external peripheral to
the other or vice a versa such as external memory, external I/O etc.
External Memory to External I/O:
In this case the DMAC operates using a read operation as its unit of operation. DMAC issues
a fly-by transfer (read) request to the bus controller and the bus controller in turn issues the
read command to the external memory and at the same time it also issues write command to
the external I/O. Simultaneously the bus controller floats the address and data bus with the
appropriate content. Hence two sequential operations (read followed by write) are replaced
by two simultaneous operations (read with write).
External I/O to External Memory:
In this case the DMAC operates using a write operation as its unit of operation. DMAC
issues a fly-by transfer (read) request to the bus controller and the bus controller in turn
issues the write command to the external memory and at the same time it also issues read
command to the external I/O. Simultaneously the bus controller floats the address and data
bus with the appropriate content. Hence two sequential operations (read followed by write)
are replaced by two simultaneous operations (read with write).
For Fly-by transfer the value configured in the transfer destination address register DMADA is
used as the address for access and it should point to the external area where as the transfer
destination address register DMASA is ignored.

2.4.3 DMA Transfer and Interrupts

By default the DMAC has the access of D-Bus. Whether the CPU is executing any function
or interrupt service routine the DMAC can request the CPU for the D-Bus by asserting D-Bus
hold request (DHREQ), the CPU in turn would respond to this DMA request by D-Bus hold
acknowledge (DHACK) granting the access of the D-Bus to the DMA.
In such situation NMI or peripheral interrupt can cancel the hold request (depending upon
configuration of LVL bits if HRCL register) and gain the access of the bus while
corresponding ISR executes. Upon execution of RETI instruction the DMA would gain
access to the D-Bus again (provided the MHALTI flag and the corresponding peripheral
interrupt flag is cleared in the ISR).
During DMA transfer, interrupts are generally not accepted until the transfer ends.
• If a DMA transfer request occurs during interrupt processing, the transfer request is
accepted and interrupt processing is stopped until the transfer is completed.
• If, as an exception, an NMI request or an interrupt request with a higher level than the hold
suppress level set by the interrupt controller occurs, DMAC temporarily cancels the transfer
request via the bus controller at a transfer unit boundary (one block) to temporarily stop the
transfer until the interrupt request is cleared. In the meantime, the transfer request is
retained internally. After the interrupt request is cleared, DMAC reissues a transfer request
to the bus controller to acquire the right to use the bus and then restarts DMA transfer.
MCU-AN-300059-E-V11 - 16 - © Fujitsu Microelectronics Europe GmbH