Multiple Interrupts - Fujitsu MB90480 Series Hardware Manual

3.4.4

Multiple Interrupts

Multiple hardware interrupt can be executed by specifying a different interrupt level for
each interrupt level setting bit (IL0 to IL2) in the interrupt control register (ICR) in
response to multiple interrupt request from the peripheral function. μDMACs cannot be
started in duplicate, however.
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Multiple interrupt operations
While an interrupt processing routine is executed, if an interrupt request with a higher level is
generated, the interrupt processing is interrupted and then the higher interrupt request is
accepted. In this case, after execution of the interrupt with the higher level is completed, the
interrupt processing being stopped is restarted. The interrupt level can be set in a range of 0 to
7, but a CPU does not accept the interrupt request when the level is set to 7.
While an interrupt is executed, if another interrupt request with the same or lower level occurs,
that interrupt request waits until the current interrupt is completed, unless ILM is changed by the
I-flag. In the interrupt processing routine, if the I-flag in the condition code register (CCR) is set
to "interrupt prohibited" (I in CCR set to "0") or the interrupt level mask register (ILM) is set to
"interrupt prohibited" (ILM set to "000"), the starting of multiple interrupts within the interrupt can
be temporarily prohibited.
Note:
μDMAC cannot be started in duplicate. All other interrupt requests and μDMAC requests have to
wait during execution of μDMAC,
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Example of multiple interrupts
Suppose a timer interrupt has priority over the A/D converter. In this case, the interrupt level of
the A/D converter is "2" whereas that of timer interrupt is "1". If a timer interrupt is generated
while an A/D converter interrupt is executed, the processing shown in the Figure 3.4-5 is
performed.
Peripheral
initialized
A/D interrupt
generated
Main process
Figure 3.4-5 Example of multiple interrupts
Main program A/D interrupt processing
Interrupt level 2
(ILM = 010)
(1)
(2)
Interrupt
Restart
(8)
restart
Timer interrupt processing
Interrupt level 1
(ILM = 001)
(3) Timer interrupt
generated
(6) A/D interrupt
processing
(7) A/D interrupt return
CHAPTER 3 INTERRUPT
(4) Timer interrupt
processing
(5) Timer interrupt
return
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