Interrupts; Table 3.2-1 Interrupt Level; Table 3.4-1 Interrupt Request And Interrupt Vector - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.4

Interrupts

The MB89120/120A series has 8 interrupt request inputs corresponding to peripheral
functions. An interrupt level can be set independently.
If an interrupt request output is enabled in the peripheral function, an interrupt request
from a peripheral function is compared with the interrupt level in the interrupt
controller. The CPU performs an interrupt operation according to how the interrupt is
accepted. In addition, with the interrupt request accepted, the CPU wakes up from
standby modes, and returns to the interrupt or normal operation.
Interrupt Requests from Peripheral Functions
Table 3.4-1 lists the interrupt requests corresponding to the peripheral functions. On acceptance
of an interrupt, execution branches to the interrupt processing routine. The contents of interrupt
vector table address corresponding to the interrupt request specifies the branch destination
address for the interrupt processing routine.
An interrupt processing level can be set for each interrupt request in the interrupt level setting
registers (ILR1, ILR2, ILR3). Three levels are available.
If an interrupt request with the same or lower level occurs during execution of an interrupt
processing routine, the latter interrupt is not normally processed until the current interrupt
processing routine completes. If interrupt requests set with the same level occur simultaneously,
the highest priority is IRQ0.

Table 3.4-1 Interrupt Request and Interrupt Vector

Interrupt request
IRQ0 (External interrupt 1-0)
IRQ1 (External interrupt 1-1)
IRQ2 (External interrupt 1-2)
IRQ3 (8/16-bit timer/counter)
IRQ4 (8-bit serial I/O)
IRQ5 (A/D converter)
IRQ6 (Timebase timer)
IRQ7 (Watch prescaler)
IRQ8 (unused)
IRQ9 (unused)
IRQA (Externel interrupt 2*)
IRQB (Unused)
40
Vector table address
Upper Lower
FFFA FFFB
H H
FFF8 FFF9
H H
FFF6 FFF7
H H
FFF4 FFF5
H H
FFF2 FFF3
H H
FFF0 FFF1
H H
FFEE FFEF
H H
FFEC FFED
H H
FFEA FFEB
H H
FFE8 FFE9
H H
FFE6 FFE7
H H
FFE4 FFE5
H H
Bit names of the
interrupt level
setting register
L01, L00
L11, L10
L21, L20
L31, L30
L41, L40
L51, L50
L61, L60
L71, L70
L81, L80
L91, L90
LA1, LA0
LB1, LB0
Priority for
simultaneous
interrupts of the
same level
High
Low