Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed; Interrupt Inhibit Instruction; Multiple Interrupts; Register Saving In Stack Upon Interrupt - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed

When internal I/O area is being asscessed, the CPU will not response to hardware interrupt immediately,
there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details.

7.4.5 Interrupt Inhibit Instruction

2
If F MC-16LX is executing interrupt inhibit instructions, the CPU will not response to hardware interrupt
request immediately, there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details.

7.4.6 Multiple Interrupts

2
The F MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another
interrupt is being processed, control is transferred to the high-level interrupt after the currently executing
instruction is completed. After processing of the high-level interrupt is completed, the original interrupt
processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is
being processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the ILM value or I flag is changed by an instruction. The extended
intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is
being processed, all other interrupt requests or extended intelligent I/O service requests are suspended.

7.4.7 Register Saving In Stack Upon Interrupt

Register saving upon interrupt
MSB
H
L

7.4.8 Precaution in Using Hardware Interrupt

When there is an hardware interrupt, the interrupt request flag should be cleared before leaving the
corresponding interrupt routine to avoid malfunction.
Some of the resources' interrupt request flag will be cleared automatically when certain register(s) is(are)
read. In this case, please read those registers to clear the interrupt request flag before leaving the interrupt
routine.
MB90580 Series
Word (16 bits)
AH
AL
DPR
DPB
PC
PS

Figure 7.4.7a Registers saved in stack

LSB
SSP (SSP value before interrupt)
ADB
PCB
7.4 Hardware Interrupt
SSP (SSP value after interrupt)
Chapter 7: Interrupt 87