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MB96300 Super Series Hardware Manual
■ Interrupt level mask register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is
accepted only when the priority of the interrupt is higher than that indicated by the ILM register and the P
flag. Highest priority interrupt is level P0 and lowest priority is level U7. Therefore, for an interrupt to be
accepted, its level value must be smaller than the current ILM value (see Figure 2.4-8 "Interrupt level register
(ILM)"). In addition, the P flag has to be considered. When an interrupt is accepted, the level value of that
interrupt is set in the P flag and ILM register. Thus, an interrupt of the same or lower priority cannot be
accepted subsequently.
15
14
ILM2
ILM1
1
0
0
0
ILM is initialized to 100
000
.
B
An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three
bits of that data are used (MOV ILM #imm, POPW PS, RETI, JCTX @A). If P=1 (in user level), any ILM
change is possible. If P=0 (priviledged level), an ILM change is only accepted, if the new value defines a
user level U0 to U7 (with P=1) or if the privileged level (P0 to P7) is increased. The lower levels of the
privileged mode P0 to P7 can not be reached by execution of an instruction from a higher level. Writing 0 to
the P flag and reducing the level with P=0 is only possible by NMI, HW-INT9 or a DSU interrupt.
Notes:
The P flag can be understood as bit extension of ILM. Then it defines the most significant bit of the the
interrupt level mask {P, ILM}.
After initialization with reset the CPU is in level P4. This disables all interrupts, including NMI, except
for the DSU. After execution of the Boot ROM program the CPU is in level U0. Peripheral interrupts are
disabled.
All privileged mode levels P0 to P7 are locked against entering or decreasing the level by an instruction.
The levels P0 to P7 can only be increased. This protects the operation of HW-INT9, NMI and DSU
operation. Only DSU can interrupt the NMI or mask its acceptance during a debug session.
The user levels U0 to U7 are backward compatible to F
not writeable in a user level.
Figure 2.4-8 Interrupt level register (ILM)
13
12
11
10
ILM0
0
0
by a reset. However, during execution of the Boot ROM program ILM is set to
B
9
8
PS: ILM
initial value after reset
value after Boot ROM execution
2
MC-16LX interrupt levels 0 to 7. The P flag is
CHAPTER 2 CPU
71
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