Multiple Interrupts; Fig. 6.9 Example Of Multiple Interrupts - Fujitsu MB90420/5 (A) Series Hardware Manual

6.4.4 Multiple Interrupts

Multiple hardware interrupts can be performed by setting different interrupt levels in the interrupt level setting
bits (IL0 to IL2) of the interrupt control register (ICR) in response to plural interrupt requests from the
resource. However, multiple EI
n Multiple interrupts
• Operation of multiple interrupts
When an interrupt request with a higher interrupt level is issued during the interrupt-processing routine, the
current interrupt handling is suspended and the higher interrupt request is accepted. When the higher-
level interrupt is terminated, interrupt handling returns to the original one. 0 to 7 can be set for the interrupt
level, but when level 7 is set, the CPU accepts no interrupt requests.
When an interrupt of equal level to or lower than the current interrupt occurs during interrupt handling, the
new interrupt request is held until the current interrupt is terminated unless the I flag or ILM. Start of
multiple interrupts during execution of interrupt handling can be temporally disabled when the I flag of the
condition code register (CCR) in the interrupt processing routine is set to interrupt disabled (CCR: I = 0) or
when the interrupt level mask register (ILM) is set to interrupt disabled (ILM = 000).
2
Note: Multiple EI OS cannot be started. During processing of EI
2
EI OS requests are all held.
• Example of multiple interrupt
As an example of the multiple interrupt handling, it is assumed that the timer interrupt is preferred to the
A/D converter interrupt, so the interrupt level of the A/D converter is set to 2 and the interrupt level of the
timer is set to 1. In this case, when a timer interrupt occurs during processing of the A/D converter
interrupt, the processing flow is shown in Figure 6.9.
Initialization of resource
A/D Interrupt occurs
Main processing resumed
• Generation of A/D interrupt
At start of the A/D converter interrupt handling, the interrupt level mask register (ILM) is set automatically to
the same value (2 in this example) as the interrupt level (ICR: IL2 to IL0) of the A/D converter. At this
time, when a level 1 or level 0 interrupt request is issued, the interrupt handling is preferred.
• Termination of interrupt handling
When interrupt processing is terminated and the return instruction (RETI) is executed, the values of the
dedicated registers (A, DPR, ADB, DTB, POB, PC, PS) saved in the stack are returned, and the interrupt
level mask register (ILM) is returned to the value before the interrupt.
INTERRUPT
2
OS cannot be started.
A/D Interrupt handling
Main program
Interrupt level 2
(ILM = 010)
(1)
(3)
(2)
Suspended
Resumed
(8) (6)
(7)

Fig. 6.9 Example of Multiple Interrupts

2
OS, other interrupt requests and other
Timer interrupt handling
Interrupt level 1
(ILM = 001)
Timer interrupt occurs
A/D Interrupt
handling
Return from A/D
interrupt
6-19
(4) Timer interrupt handling
(5) Return from timer interrupt