Interrupts - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART

15.5 Interrupts

The UART has receive interrupts and send interrupts. Interrupt requests are generated
in the following cases:
• When receive data is set in the input-data register (SIDR0-3) or when a receive error
occurs
• When send data is transferred from the output-data register (SODR0-3) to the send-
shift register
UART interrupts
Table 15.5-1 "UART interrupt control bit and interrupt sources" shows the UART interrupt
control bit and interrupt sources.
Table 15.5-1 UART interrupt control bit and interrupt sources
Interrupt
Send or
request flag
receive
bit
RDRF
ORE
Receive
FRE
PE
Send TDRE
o: Used bit
x: Unused bit
Receive interrupt
In receive mode, if data reception is completed (SSR0-3: RDRF), if an overrun error occurs
(SSR0-3: ORE), if a framing error occurs (SSR0-3: FRE), or if a parity error occurs (SSR0-3:
PE), the corresponding flag bit is set to 1. If the receive interrupt is enabled (SSR0-3: RIE = 1)
when any of these flag bits is 1, a receive-interrupt request is output to the interrupt controller.
The receive data full flag (SSR0-3: RDRF) is automatically cleared to 0 when the input-data
register (SIDR0-3) is read. When the REC bit of the control register (SCR0-3) is set to 0, the
receive-error flags (SSR0-3: PE, ORE, FRE) are cleared to 0.
Send interrupt
When send data is transferred from the output-data register (SODR0-3) to the transfer shift
register, the TDRE bit of the status register (SSR0-3) is set to 1. If the send interrupt is enabled
(SSR0-3: TIE = 1), a send-interrupt request is output to the interrupt controller.
322
Operation mode
Interrupt source
0 1 2
Receive data is
o o o loaded into the buffer
(SIDR0-3)
An overrun error
o o o
occurs
A framing error
o o x
occurs
o x x A parity error occurs
Send buffer
o o o
(SODR0-3) is empty
Interrupt Interrupt
source request flag
enable bit clear
Receive data is
read
SSR0-3:RIE
The receive-
error flag-clear
bit (SCR0-3:
REC) is set to 0
Send data is
SSR0-3:TIE
written