Avaya DEFINITY Server CSI Maintenance Manual page 1541

PROCR (RISC Processor Circuit Pack TN2402/TN798)
Table 428. Test #82 Processor Bus Time-out Exception Test
Error Test
Code Result
100 ABORT The test did not complete within the allowable time period.
2500 ABORT Internal system error
FAIL The interrupt was not detected or acted upon.
PASS The interrupt was correctly detected. The RISC Processor is functioning
correctly.
Processor Cache Test (#895)
This test is a nondestructive test. This test overwrites the contents in the
Instruction and Data Caches, requiring them to be refilled during normal
execution.
This test verifies that the Processor Instruction and Data Caches are functional.
Some errors in the caches will simply reduce performance by forcing instructions
or data to be read from memory more often than would normally be necessary. In
any case, cache problems are serious and the Processor circuit pack must be
replaced as soon as possible if they are detected.
Table 429. Test #895 Processor Cache Test
Error Test
Code Result
100 ABORT
2500 ABORT
FAIL
PASS
555-233-119
Description/ Recommendation
1. Retry the command.
1. Repeat the command at 1-minute intervals a maximum of 5 times.
2. If the test continues to fail, the Processor circuit pack should be replaced.
The replacement must have enough memory for this system.
Description/ Recommendation
The test did not complete within the allowable time period.
1. Retry the command.
Internal system error
1. Retry the command.
The Processor cache is not functioning correctly.
1. Replace the Processor circuit pack immediately.
The cache portion of the Processor circuit pack is operating correctly.
Continued on next page
Continued on next page
Issue 5 October 2002
1541