Tdm Bus Clock Circuit Status Inquiry Test - Avaya DEFINITY Server CSI Maintenance Manual

TDM-CLK (TDM Bus Clock)
Notes:
a. Refer to
tests.
b. Refer to
test.
c. Refer to

TDM Bus Clock Circuit Status Inquiry Test (#148)

The TDM Bus Clock circuitry is checked for sanity. Any problems that are found
are reported via error codes
Table 491. TEST #148 TDM Bus Clock Circuit Status Inquiry Test
Error Test
Code Result
None ABORT
1001
2000 ABORT
2100 ABORT
1 FAIL
555-233-119
''XXX-BD (Common Port Circuit Pack)''
''TONE-BD (Tone-Clock Circuit Pack)''
''TONE-PT (Tone Generator)''
Description/ Recommendation
The system could not allocate the necessary resources for the test.
1. Wait 1 minute, and retry the test.
Response to the test request was not received within the allowable time
period.
System resources required to run this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5 times.
This error means the Tone-Clock circuit pack framing verification firmware
reports an error in the clock synchronization signal coming into this Port
Network.
1. If the Tone-Clock circuit pack reporting the problem is a master clock,
then the system synchronization reference is providing a bad timing
source. Refer to SYNC (Synchronization) Maintenance documentation
to change the system synchronization reference.
2. If the Tone-Clock circuit pack is a slave clock, then the EI to which it is
listening is providing a bad timing source. Follow the diagnostic
procedures specified for TDM-CLK Error Code 2305.
3. If no problem can be found with the incoming synchronization signal,
replace the Tone-Clock circuit pack.
for descriptions of these
for a description of this
for descriptions of these tests.
Continued on next page
Issue 5 October 2002
1673