Avaya DEFINITY Server CSI Maintenance Manual page 1638

Maintenance Objects
Receive FIFO Overflow Error
Counter Test (#625)
This test is nondestructive. This test reads and clears the BRI port's Receive FIFO
Overflow error counter maintained on the TBRI-BD circuit pack. This counter is
incremented by the circuit pack when it detects an overflow of its receive buffers.
The test passes if the value of the counter is 0 (that is, the error is cleared). If the
counter is non-zero, the test fails, and the value of the counter is displayed in the
Error Code field.
This error can occur if signaling frames are being received from the Packet Bus at
a rate sufficient to overflow the receive buffers on the circuit pack for a port OR if a
hardware fault is causing the receive buffers not to be emptied properly by the
circuit pack. This test is useful for verifying the repair of the problem.
Table 477. TEST #625 Receive FIFO Overflow Error Counter Test
Error Test
Code Result
2000 ABORT
2012 ABORT
2100 ABORT
value FAIL
PASS
1638
Issue 5 October 2002
Description/ Recommendation
Response to the test was not received from the circuit pack within the
allowable time period.
1. If the test aborts repeatedly a maximum of 5 times, reset the circuit
pack with the busyout board PCSS and reset board PCSS
commands.
2. If the test aborts again, replace the circuit pack.
Internal system error
Could not allocate the necessary system resources to run this test.
1. Retry the command at 1-minute intervals a maximum of 5 times.
The TBRI-BD circuit pack is still detecting errors of this type. The Error
Code field contains the value of this counter.
1. Retry the command at 1-minute intervals a maximum of 5 times.
2. If the test continues to fail, run the Long Test Sequence and pay
particular attention to the Looparound Tests (#618 and #619). See the
repair procedures for the executed test if it fails. Otherwise, go to the
next step.
3. Replace the circuit pack.
The Receive FIFO Overflow error counter was read correctly and has a
value of 0.
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