Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 244

7-3 Generic Performance Counter Data Register Fields . . . . . . . . . . . . . . . . . . . . 2:157
7-4 Generic Performance Counter Configuration Register Fields (PMC[4]..PMC[p]) . . . . . . 2:157
7-5 Reading Performance Monitor Data Registers . . . . . . . . . . . . . . . . . . . . . . . 2:158
7-6 Performance Monitor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:159
7-7 Performance Monitor Overflow Register Fields (PMC[0]...PMC[3]) . . . . . . . . . . . . . 2:161
8-1 Writing of Interruption Resources by Vector . . . . . . . . . . . . . . . . . . . . . . . . . 2:166
8-2 ISR Values on Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:168
8-3 ISR.code Fields on Intel
8-4 Interruption Vectors Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . 2:171
9-1 Intercept Code Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:234
9-2 Segment Prefix Override Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:234
9-3 Gate Intercept Trap Code Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:235
9-4 System Flag Intercept Instruction Trap Code Instruction Identifier . . . . . . . . . . . . . 2:236
10-1 IA-32 System Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:240
10-2 IA-32 System Segment Register Fields (LDT, GDT, TSS) . . . . . . . . . . . . . . . . . 2:242
10-3 IA-32 EFLAG Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:244
10-4 IA-32 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:247
10-5 IA-32 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:254
10-6 Instruction Cache Coherency Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:265
10-7 IA-32 Load/Store Sequentiality and Ordering . . . . . . . . . . . . . . . . . . . . . . . . 2:265
10-8 IA-32 Interruption Vector Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:275
10-9 IA-32 Interruption Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:275
11-1 FIT Entry Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:288
11-2 GR38 Reset Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:290
11-3 function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:291
11-4 status Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:292
11-5 Geographically Significant Processor Identifier Fields . . . . . . . . . . . . . . . . . . . 2:293
11-6 state Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:294
11-7 Processor State Parameter Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:299
11-8 Software Recovery Bits in Processor State Parameter . . . . . . . . . . . . . . . . . . . 2:301
11-9 PSP Bit Settings for Unconsumed Data-poisoning Events on MCA. . . . . . . . . . . . . 2:302
11-10 NaT Bits for Saved GRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:305
11-11 function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:305
11-12 Processor State Parameter Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:308
11-13 function Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:310
11-14 PMI Events and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:311
11-15 PMI Message Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:311
11-16 Virtual Processor Descriptor (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:326
11-17 Virtual Processor Descriptor (VPD) – VPSR . . . . . . . . . . . . . . . . . . . . . . . . 2:328
11-18 Virtual Processor Descriptor (VPD) – VCR[0-127] . . . . . . . . . . . . . . . . . . . . . 2:329
11-19 Virtualization Acceleration Control (vac) Fields . . . . . . . . . . . . . . . . . . . . . . . 2:329
11-20 Virtualization Disable Control (vdc) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 2:330
11-21 IVA Settings after PAL Virtualization-related Procedures and Services . . . . . . . . . . . 2:332
11-22 PAL Virtualization Intercept Handoff Cause (GR24) . . . . . . . . . . . . . . . . . . . . 2:334
11-23 Global Virtualization Optimizations Summary . . . . . . . . . . . . . . . . . . . . . . . . 2:336
11-24 Synchronization Requirements for Virtualization Opcode Optimization . . . . . . . . . . . 2:336
11-25 Behavior of Guest MOV-from-AR.ITC Instruction in Virtual Environment . . . . . . . . . . 2:337
11-26 Virtualization Accelerations Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:338
11-27 Detection of Virtual External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:339
11-28 Synchronization Requirements for Virtual External Interrupt Optimization . . . . . . . . . 2:339
11-29 Interruptions when Virtual External Interrupt Optimization is Enabled . . . . . . . . . . . 2:340
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Itanium Traps . . . . . . . . . . . . . . . . . . . . . . . . . . 2:170
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Intel
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Itanium Architecture Software Developer's Manual, Rev. 2.3