Figure 11.5 Examples Of Counter And Register Operations - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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Figure 11.5 shows examples of counter and register operations.
×2
TDDR
(Td)
TBRU
TBRV
TBRW
(TBR)
TPBR
(1/2 period)
×2
TDDR
(Td)
TDDR
(Td)
TDCNT

Figure 11.5 Examples of Counter and Register Operations

Initial Settings: In the operating modes, there are five registers that require initialization.
Make the following register settings before setting the operating mode with bits MD1 and MD0 in
the timer mode register (TMDR).
Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the
timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set
{TPBR value + 2Td} in the timer period data register (TPDR).
TGRUU
+
TGRVU
(TBR + 2Td)
TGRWU
TGRU
+
TGRV
(TBR + Td)
TGRW
TGRUD
TGRVD
(TBR)
TGRWD
(1/2 period + 2Td)
+
TPDR
TCNT
(2Td)
Up-count → compare match → halt
Section 11 Motor Management Timer (MMT)
TCNT
Up-count → compare
Compared during
match → down-count
up-count
Down-count → compare
Compared during
match → up-count
down-count
Rev. 6.00 Mar 15, 2006 page 257 of 570
Compared during
up-count
Constantly
compared
Compared during
down-count
REJ09B0211-0600

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