ST STM32L4x6 Reference Manual page 1162

Inter-integrated circuit (I2C) interface
Bit 15 RXDMAEN: DMA reception requests enable
Bit 14 TXDMAEN: DMA transmission requests enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 ANFOFF: Analog noise filter OFF
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bits 11:8 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter
will filter spikes with a length of up to DNF[3:0] * t
Note: If the analog filter is also enabled, the digital filter is added to the analog filter.
Bit 7 ERRIE: Error interrupts enable
Note: Any of these errors generate an interrupt:
Bit 6 TCIE: Transfer Complete interrupt enable
Note: Any of these events will generate an interrupt:
Bit 5 STOPIE: STOP detection Interrupt enable
Bit 4 NACKIE: Not acknowledge received Interrupt enable
Bit 3 ADDRIE: Address match Interrupt enable (slave only)
1162/1693
0: DMA mode disabled for reception
1: DMA mode enabled for reception
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
0: Analog noise filter enabled
1: Analog noise filter disabled
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to 1 t
...
1111: digital filter enabled and filtering capability up to15 t
This filter can only be programmed when the I2C is disabled (PE = 0).
0: Error detection interrupts disabled
1: Error detection interrupts enabled
Arbitration Loss (ARLO)
Bus Error detection (BERR)
Overrun/Underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
Transfer Complete (TC)
Transfer Complete Reload (TCR)
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
I2CCLK
DocID024597 Rev 3
I2CCLK
I2CCLK
RM0351