Setting The Main Clock Oscillation Stabilization Waiting Period; Switching The Machine Clock - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

In addition, the instruction execution time when the CPU intermittent operation function is used can be
calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource,
and external bus access multiplied by the number of pause cycles) to the normal execution time.
Peripheral clock
CPU clock

6.4.7 Setting the main clock oscillation stabilization waiting period

The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for wake-
up from stop mode and hardware standby mode. The oscillation stabilization waiting period should be set
in accordance with the type and characteristics of the oscillation circuit and oscillator connected to the X0
and X1 pins.
These bits are not initialized in the event of a reset, except for a power-on reset. If a power-on reset is
generated, these bits are initialized to "11". Therefore, when power is first applied, the main clock
lation stabilization waiting period is set to approximately a count of 2
tion.

6.4.8 Switching the machine clock

Main clock/PLL clock switching
Switching between the main clock and the PLL clock is accomplished by writing to the MCS bit in the
CKSCR register.
If the MCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the PLL
clock, once the PLL clock oscillation stabilization waiting period passes (2
If the MCS bit is overwritten from a "0" to a "1", the machine clock switches from the PLL clock to the main
clock, at the point when the edges of the PLL clock and the main clock match (after 1 to 8 PLL clocks).
Because the machine clock does not switch immediately after the MCS bit is overwritten, when
forming operations on resources that depend on the machine clock, always reference the MCM bit and
make sure that the machine clock was switched before performing the operation on the resource.
Main clock/sub-clock switching
Switching between the main clock and the sub-clock is accomplished by writing to the SCS bit in the
CKSCR register.
If the SCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the sub-
clock when the sub-clock edge is detected.
If the SCS bit is overwritten from a "0" to a "1", the machine clock switches from the sub-clock to the main
clock after the main clock oscillation stabilization waiting period elapses.
Because the machine clock does not switch immediately after the SCS bit is overwritten, when performing
operations on resources that depend on the machine clock, always reference the SCM bit and make sure
that the machine clock was switched before performing the operation on the resource.
MB90580 Series
Intermittent operation pause cycle
Internal bus activation cycle
18
pulses of the source
11
machine clocks).
Chapter 6: Low Power Control Circuit
6.4 Operations
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