Figure 6.4 Watchdog Timer Clear And Interval Time (For A 10 Mhz Source Oscillation) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4
6. Operation of Watchdog Timer
The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
n Watchdog Timer Operation
l Activating watchdog timer
• The watchdog timer is activated by writing "0101
watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset.
• Once activated, the watchdog timer cannot be stopped other than by a reset.
Clearing watchdog timer
l
• The watchdog timer counter is cleared by writing "0101
watchdog control register (WDTC: WTE3 to WTE0) for the second or subsequent times after
a reset.
• If the counter is not cleared within the interval time of the watchdog timer, the counter
overflows and the watchdog timer generates an internal reset signal for four-instruction
cycles.
Interval time of watchdog timer
l
The interval time changes depending on when the watchdog timer is cleared.
Figure 6.4 shows the relationship between the watchdog timer clear timing and the interval time.
Minimum time
Maximum time

Figure 6.4 Watchdog Timer Clear and Interval Time (For a 10 MHz source oscillation)

MB89620 series
Count clock output of
the timebase timer
Watchdog clear
1-bit watchdog
counter
Watchdog reset
Count clock output of
the timebase timer
Watchdog clear
1-bit watchdog
counter
Watchdog reset
" to the watchdog control bits in the
B
" to the watchdog control bits in the
B
209.7 ms
Overflow
419.4 ms
CHAPTER 6 WATCHDOG TIMER
Overflow
133