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F2MC-8L Family series
Fujitsu F2MC-8L Family series Manuals
Manuals and User Guides for Fujitsu F2MC-8L Family series. We have
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Fujitsu F2MC-8L Family series manual available for free PDF download: Hardware Manual
Fujitsu F2MC-8L Family series Hardware Manual (110 pages)
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 0.63 MB
Table of Contents
Table of Contents
3
1 General
7
Features
7
Product Series
8
Table 1-1 Types and Functions of MB89950 Series of Microcontrollers
8
Block Diagram
9
Fig. 1.1 Block Diagram (MB89953)
9
Pin Assignment
10
Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, Pitch: 0.65 MM)
10
Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, Pitch: 0.8 MM)
11
Pin Description
12
Table 1-2 Pin Description
12
Table 1-3 Pin Description for External ROM
13
Fig. 1.4 I/O Circuits
14
Handling Devices
16
2 Hardware Configuration
17
Cpu
18
Memory Space
18
Fig. 2.1 Memory Space of MB89950 Series Microcontrollers
18
Table 2-1 Table of Reset and Interrupt Vectors
19
Arrangement of 16-Bit Data in Memory Space
20
Fig. 2.2 Arrangement of 16 Bit Data in Memory Space
20
Fig. 2.3 Arrangement of 16 Bit Data During Execution of Instruction
20
Internal Registers in CPU
21
Fig. 2.4 Structure of Processor Status
22
Fig. 2.5 Rule for Translating Real Addresses at General-Purpose Register Area
22
Fig. 2.6 Register Bank Configuration
23
Clock Control Block
24
Table 2-2 Operating Mode of Low-Power Consumption Modes
26
Table 2-3 Selection of Oscillation Stabilization Time
27
Table 2-4 Sources of Reset
29
Interrupt Controller
30
Fig. 2.7 Interrupt-Processing Flowchart
32
Peripherals
33
I/O Ports
33
Table 2-5 List of Port Functions
33
Fig. 2.9 Port
37
Fig. 2.10 Port 4
39
8-Bit PWM Timer (Timer 1)
40
Fig. 2.11 Timer Operation
43
Fig. 2.12 PWM Pulse Output
44
Pulse-Width Count Timer (Timer 2)
45
Fig. 2.13 Measurement of High Pulse Width
50
Fig. 2.14 Operation of Noise Clearing Circuit
51
Uart
52
Table 2-6 Operation Modes of UART
61
Fig. 2.15 RDRF Flag Set Timing
61
Fig. 2.16 ORFE Flag Set Timing
62
Fig. 2.17 TDRE Flag Set Timing
62
Fig. 2.18 Transfer Data Format (Synchronous Transfer)
62
Table 2-7 Clock Division Ratio
63
Table 2-8 Input Clock of Baud Rate Generator
63
Table 2-9 Selection of Baud Rate (When Dedicated Baud Rate Generate Used)
64
8-Bit Serial I/O
65
Fig. 2.19 Shift Start/Stop Timing
70
Fig. 2.20 Input/Output Shift Timing
70
External Interrupt
71
LCD Controller/Driver
74
Fig. 2.21 LCD Controller /Driver Block Diagram
74
Fig. 2.22 Example of Waveform at Pin Corresponding to the RAM Data for Display
79
Fig. 2.23 Example of Waveform at Pin Corresponding to the RAM Data for Display
80
Fig. 2.24 Example of Waveform at Pin Corresponding to the RAM Data for Display
81
Fig. 2.25 Connection Examples for Supply Power for Driving LCD
82
Fig. 2.26 Built-In Voltage Dividing Resistors
83
Time-Base Timer
84
Watchdog Timer Reset
86
3 Operation
88
Clock Pulse Generator
89
Fig. 3.1 Clock Pulse Generator
89
Reset
90
Reset Operation
90
Fig. 3.2 Outline of Reset Operation
90
Fig. 3.3 Reset Vector Structure
90
Reset Sources
91
Interrupt
92
Fig. 3.4 Interrupt-Processing Flowchart
92
Table 3-1 Interrupt Sources and Interrupt Vectors
93
Low-Power Consumption Modes
94
Table 3-2 Low-Power Consumption Mode at each Clock Mode
94
Pin States for Sleep, Stop and Reset
95
Pin States for Sleep, Stop, and Reset
95
Table 3-3 Pin State of MB89950
95
4 Instructions
96
Legend
97
Transfer Instructions
98
Operation Instructions
99
Branch Instructions
100
Other Instructions
101
F 2 MC-8L Family Instruction Map
102
5 Mask Options
103
Table 5-1 Mask Options
104
Table 5-2 Recommended Port/Segment Mask Option Combinations
104
Appendix
105
Appendix A I/O Map
106
Appendix B Writing EPROM
108
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