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Fujitsu MB95630H Series Hardware Manual

Fujitsu MB95630H Series Hardware Manual (644 pages)

8-BIT MICROCONTROLLER New 8FX  
Brand: Fujitsu | Category: Recording Equipment | Size: 8.25 MB
Table of contents
Sample Programs5................................................................................................................................................................
How To Use This Manual6................................................................................................................................................................
Table Of Contents9................................................................................................................................................................
Chapter 1 Memory Access Mode21................................................................................................................................................................
Memory Access Mode22................................................................................................................................................................
Chapter 2 Cpu23................................................................................................................................................................
Dedicated Registers24................................................................................................................................................................
Register Bank Pointer (rp)26................................................................................................................................................................
Direct Bank Pointer (dp)27................................................................................................................................................................
Condition Code Register (ccr)29................................................................................................................................................................
General-purpose Register31................................................................................................................................................................
Placement Of 16-bit Data In Memory33................................................................................................................................................................
Clock Controller35................................................................................................................................................................
Overview36................................................................................................................................................................
Clock Modes40................................................................................................................................................................
Standby Mode41................................................................................................................................................................
Oscillation Stabilization Wait Time44................................................................................................................................................................
Registers47................................................................................................................................................................
System Clock Control Register (sycc)48................................................................................................................................................................
Pll Control Register (pllc)49................................................................................................................................................................
Oscillation Stabilization Wait Time Setting Register (watr)50................................................................................................................................................................
Standby Control Register (stbc)52................................................................................................................................................................
System Clock Control Register 2 (sycc2)54................................................................................................................................................................
System Clock Control Register 2 (sycc)54................................................................................................................................................................
Standby Control Register 2 (stbc2)56................................................................................................................................................................
Standby Control Register 2 (stbc)56................................................................................................................................................................
Operations In Low Power Consumption Mode (standby Mode)61................................................................................................................................................................
Notes On Using Standby Mode62................................................................................................................................................................
Sleep Mode68................................................................................................................................................................
Stop Mode69................................................................................................................................................................
Time-base Timer Mode71................................................................................................................................................................
Watch Mode73................................................................................................................................................................
Clock Oscillator Circuit74................................................................................................................................................................
Overview Of Prescaler75................................................................................................................................................................
Configuration Of Prescaler76................................................................................................................................................................
Operation Of Prescaler77................................................................................................................................................................
Notes On Using Prescaler79................................................................................................................................................................
Chapter 4 Reset81................................................................................................................................................................
Reset Operation82................................................................................................................................................................
Register86................................................................................................................................................................
Reset Source Register (rsrr)87................................................................................................................................................................
Notes On Using Reset90................................................................................................................................................................
Chapter 5 Interrupts91................................................................................................................................................................
Interrupts92................................................................................................................................................................
Interrupt Level Setting Registers (ilr0 To Ilr5)93................................................................................................................................................................
Interrupt Level Setting Registers (ilr0 To Ilr)93................................................................................................................................................................
Interrupt Processing95................................................................................................................................................................
Nested Interrupts97................................................................................................................................................................
Interrupt Processing Time98................................................................................................................................................................
Stack Operation During Interrupt Processing99................................................................................................................................................................
Interrupt Processing Stack Area100................................................................................................................................................................
Chapter 6 I/o Port101................................................................................................................................................................
I/o Port101................................................................................................................................................................
Configuration And Operations103................................................................................................................................................................
Time-base Timer107................................................................................................................................................................
Configuration109................................................................................................................................................................
Interrupt111................................................................................................................................................................
Operations And Setting Procedure Example112................................................................................................................................................................
Time-base Timer Control Register (tbtc)116................................................................................................................................................................
Notes On Using Time-base Timer118................................................................................................................................................................
Chapter 8 Hardware/software Watchdog Timer126................................................................................................................................................................
Watchdog Timer Control Register (wdtc)127................................................................................................................................................................
Notes On Using Watchdog Timer129................................................................................................................................................................
Watch Prescaler Control Register (wpcr)140................................................................................................................................................................
Notes On Using Watch Prescaler142................................................................................................................................................................
Chapter 10 Wild Register Function143................................................................................................................................................................
Operations147................................................................................................................................................................
Wild Register Data Setting Registers (wrdr0 To Wrdr2)149................................................................................................................................................................
Wild Register Address Setting Registers (wrar0 To Wrar2)150................................................................................................................................................................
Wild Register Address Compare Enable Register (wren)151................................................................................................................................................................
Wild Register Data Test Setting Register (wror)152................................................................................................................................................................
Typical Hardware Connection Example153................................................................................................................................................................
Channel161................................................................................................................................................................
Pins162................................................................................................................................................................
Operation Of Interval Timer Function (one-shot Mode)164................................................................................................................................................................
Operation Of Interval Timer Function (continuous Mode)166................................................................................................................................................................
Operation Of Interval Timer Function (free-run Mode)168................................................................................................................................................................
Operation Of Pwm Timer Function (fixed-cycle Mode)170................................................................................................................................................................
Operation Of Pwm Timer Function (variable-cycle Mode)172................................................................................................................................................................
Operation Of Pwc Timer Function174................................................................................................................................................................
Operation Of Input Capture Function176................................................................................................................................................................
Operation Of Noise Filter178................................................................................................................................................................
Bit Composite Timer Status Control Register 0 (tn0cr0/tn1cr0)180................................................................................................................................................................
Bit Composite Timer Status Control Register 1 (tn0cr1/tn1cr1)183................................................................................................................................................................
Bit Composite Timer Timer Mode Control Register (tmcrn)187................................................................................................................................................................
Bit Composite Timer Data Register (tn0dr/tn1dr)190................................................................................................................................................................
Notes On Using 8/16-bit Composite Timer193................................................................................................................................................................
Chapter 12 External Interrupt Circuit195................................................................................................................................................................
Channels198................................................................................................................................................................
External Interrupt Control Register (eic)204................................................................................................................................................................
Notes On Using External Interrupt Circuit206................................................................................................................................................................
Chapter 13 Interrupt Pin Selection Circuit207................................................................................................................................................................
Operation211................................................................................................................................................................
Interrupt Pin Selection Circuit Control Register (wicr)213................................................................................................................................................................
Notes On Using Interrupt Pin Selection Circuit216................................................................................................................................................................
Chapter 14 Lin-uart217................................................................................................................................................................
Reload Counter221................................................................................................................................................................
Timing Of Receive Interrupt Generation And Flag Set229................................................................................................................................................................
Timing Of Transmit Interrupt Generation And Flag Set231................................................................................................................................................................
Lin-uart Baud Rate233................................................................................................................................................................
Baud Rate Setting235................................................................................................................................................................
Operations Of Lin-uart And Lin-uart Setting Procedure Example241................................................................................................................................................................
Operations In Asynchronous Mode (operating Mode 0, 1)243................................................................................................................................................................
Operations In Synchronous Mode (operating Mode 2)247................................................................................................................................................................
Operations In Synchronous Mode (operating Mode)247................................................................................................................................................................
Operations Of Lin Function (operating Mode 3)251................................................................................................................................................................
Operations Of Lin Function (operating Mode)251................................................................................................................................................................
Serial Pin Direct Access254................................................................................................................................................................
Bidirectional Communication Function (normal Mode)255................................................................................................................................................................
Master/slave Mode Communication Function (multiprocessor Mode)257................................................................................................................................................................
Lin Communication Function260................................................................................................................................................................
Examples Of Lin-uart Lin Communication Flow Chart (operating Mode 3)261................................................................................................................................................................
Lin-uart Serial Control Register (scr)264................................................................................................................................................................
Lin-uart Serial Mode Register (smr)266................................................................................................................................................................
Lin-uart Serial Status Register (ssr)268................................................................................................................................................................
Lin-uart Receive Data Register/lin-uart Transmit Data Register (rdr/tdr)270................................................................................................................................................................
Lin-uart Extended Status Control Register (escr)272................................................................................................................................................................
Lin-uart Extended Communication Control Register (eccr)275................................................................................................................................................................
Lin-uart Baud Rate Generator Registers 1, 0 (bgr1, Bgr0)277................................................................................................................................................................
Notes On Using Lin-uart278................................................................................................................................................................
Chapter 15 8/10-bit A/d Converter283................................................................................................................................................................
Bit A/d Converter Control Register 1 (adc1)293................................................................................................................................................................
Bit A/d Converter Control Register 2 (adc2)295................................................................................................................................................................
Bit A/d Converter Data Register (upper/lower) (addh/addl)297................................................................................................................................................................
Notes On Using 8/10-bit A/d Converter298................................................................................................................................................................
Chapter 16 Low-voltage Detection Reset Circuit301................................................................................................................................................................
Lvd Reset Voltage Selection Id Register (lvdr)307................................................................................................................................................................
Chapter 17 Clock Supervisor Counter309................................................................................................................................................................
Clock Monitoring Data Register (cmdr)319................................................................................................................................................................
Clock Monitoring Control Register (cmcr)320................................................................................................................................................................
Notes On Using Clock Supervisor Counter322................................................................................................................................................................
Chapter 18 8/16-bit Ppg325................................................................................................................................................................
Bit Ppg Independent Mode333................................................................................................................................................................
Bit Prescaler + 8-bit Ppg Mode335................................................................................................................................................................
Bit Ppg Mode337................................................................................................................................................................
Bit Ppg Timer N1 Control Register (pcn1)341................................................................................................................................................................
Bit Ppg Timer N0 Control Register (pcn0)343................................................................................................................................................................
Bit Ppg Timer N1/n0 Cycle Setup Buffer Register (ppsn1/ppsn0)345................................................................................................................................................................
Bit Ppg Timer N1/n0 Duty Setup Buffer Register (pdsn1/pdsn0)346................................................................................................................................................................
Bit Ppg Start Register (ppgs)347................................................................................................................................................................
Bit Ppg Output Reverse Register (revc)349................................................................................................................................................................
Notes On Using 8/16-bit Ppg351................................................................................................................................................................
Chapter 19 16-bit Ppg Timer353................................................................................................................................................................
Bit Ppg Downcounter Register (upper/lower) (pdcrhn/pdcrln)365................................................................................................................................................................
Bit Ppg Cycle Setting Buffer Register (upper/ Lower) (pcsrhn/pcsrln)366................................................................................................................................................................
Bit Ppg Duty Setting Buffer Register (upper/lower) (pduthn/pdutln)367................................................................................................................................................................
Bit Ppg Status Control Register (upper) (pcnthn)368................................................................................................................................................................
Bit Ppg Status Control Register (lower) (pcntln)370................................................................................................................................................................
Notes On Using 16-bit Ppg Timer372................................................................................................................................................................
Chapter 20 16-bit Reload Timer373................................................................................................................................................................
Internal Clock Mode383................................................................................................................................................................
Event Count Mode387................................................................................................................................................................
Bit Reload Timer Control Status Register (upper) (tmcsrhn)390................................................................................................................................................................
Bit Reload Timer Control Status Register (lower) (tmcsrln)392................................................................................................................................................................
Bit Reload Timer Timer Register (upper/lower) (tmrhn/tmrln)394................................................................................................................................................................
Bit Reload Timer Reload Register (upper/lower) (tmrlrhn/tmrlrln)395................................................................................................................................................................
Notes On Using 16-bit Reload Timer396................................................................................................................................................................
Chapter 21 Multi-pulse Generator397................................................................................................................................................................
Block Diagram401................................................................................................................................................................
Bit Mpg Output Data Register (upper/lower) (opdur/opdlr)413................................................................................................................................................................
Operation Of Position Detection414................................................................................................................................................................
Operation Of Data Write Control Unit416................................................................................................................................................................
Operation Of 16-bit Mpg Output Data Buffer Register (upper/lower Opdbrhx/opdbrlx)420................................................................................................................................................................
Operation Of Data Transfer Of 16-bit Mpg Output Data Register (upper/lower)422................................................................................................................................................................
At Opdbrh0 And Opdbrl0 Write424................................................................................................................................................................
At 16-bit Reload Timer Underflow425................................................................................................................................................................
At Position Detection427................................................................................................................................................................
At Position Detection And Timer Underflow429................................................................................................................................................................
At Position Detection Or Timer Underflow432................................................................................................................................................................
At One-shot Position Detection434................................................................................................................................................................
When One-shot Position Detection And Reload Timer Underflow435................................................................................................................................................................
When One-shot Position Detection Or Reload Timer Underflow436................................................................................................................................................................
Operation Of Dtti Input Control437................................................................................................................................................................
Operation Of Noise Cancellation Function440................................................................................................................................................................
Operation Of 16-bit Timer441................................................................................................................................................................
Bit Mpg Output Control Register (upper) (opcur)447................................................................................................................................................................
Bit Mpg Output Control Register (upper)447................................................................................................................................................................
Bit Mpg Output Control Register (lower) (opclr)449................................................................................................................................................................
Bit Mpg Output Control Register (lower)449................................................................................................................................................................
Bit Mpg Output Data Register (upper) (opdur)452................................................................................................................................................................
Bit Mpg Output Data Register (upper)452................................................................................................................................................................
Bit Mpg Output Data Register (lower) (opdlr)454................................................................................................................................................................
Bit Mpg Output Data Register (lower)454................................................................................................................................................................
Bit Mpg Output Data Buffer Register (upper/lower) (opdbrhx/opdbrlx)455................................................................................................................................................................
Bit Mpg Output Data Buffer Register (upper) (opdbrhx)456................................................................................................................................................................
Bit Mpg Output Data Buffer Register (lower) (opdbrlx)458................................................................................................................................................................
Bit Mpg Output Data Buffer Register (lower)458................................................................................................................................................................
Bit Mpg Input Control Register (upper/lower) (ipcur/ipclr)460................................................................................................................................................................
Bit Mpg Input Control Register (upper) (ipcur)461................................................................................................................................................................
Bit Mpg Input Control Register (upper)461................................................................................................................................................................
Bit Mpg Input Control Register (lower) (ipclr)463................................................................................................................................................................
Bit Mpg Input Control Register (lower)463................................................................................................................................................................
Bit Mpg Compare Clear Register (upper/lower) (cpcur/cpclr)465................................................................................................................................................................
Bit Mpg Timer Buffer Register (upper/lower) (tmbur/tmblr)466................................................................................................................................................................
Bit Mpg Timer Control Status Register (tcsr)467................................................................................................................................................................
Bit Mpg Noise Cancellation Control Register (nccr)469................................................................................................................................................................
Bit Mpg Noise Cancellation Control Register469................................................................................................................................................................
Notes On Using Multi-pulse Generator470................................................................................................................................................................
Sample Program For Multi-pulse Generator472................................................................................................................................................................
Chapter 22 Uart/sio475................................................................................................................................................................
Operations In Operation Mode 0483................................................................................................................................................................
Operations In Operation Mode 1490................................................................................................................................................................
Uart/sio Serial Mode Control Register 1 (smc1n)497................................................................................................................................................................
Uart/sio Serial Mode Control Register 2 (smc2n)499................................................................................................................................................................
Uart/sio Serial Status And Data Register (ssrn)501................................................................................................................................................................
Uart/sio Serial Input Data Register (rdrn)503................................................................................................................................................................
Uart/sio Serial Output Data Register (tdrn)504................................................................................................................................................................
Chapter 23 Uart/sio Dedicated Baud Rate Generator505................................................................................................................................................................
Uart/sio Dedicated Baud Rate Generator Prescaler Select Register (pssrn)510................................................................................................................................................................
Uart/sio Dedicated Baud Rate Generator Baud Rate Setting Register (brsrn)511................................................................................................................................................................
Chapter 24 I 2 C Bus Interface517................................................................................................................................................................
Function To Wake Up The Mcu From Standby Mode531................................................................................................................................................................
Sector/bank Configuration554................................................................................................................................................................
Invoking Flash Memory Automatic Algorithm555................................................................................................................................................................
Checking Automatic Algorithm Execution Status557................................................................................................................................................................
Data Polling Flag (dq7)559................................................................................................................................................................
Data Polling Flag (dq)559................................................................................................................................................................
Toggle Bit Flag (dq6)561................................................................................................................................................................
Toggle Bit Flag (dq)561................................................................................................................................................................
Execution Timeout Flag (dq5)562................................................................................................................................................................
Execution Timeout Flag (dq)562................................................................................................................................................................
Sector Erase Timer Flag (dq3)563................................................................................................................................................................
Sector Erase Timer Flag (dq)563................................................................................................................................................................
Toggle Bit2 Flag (dq2)564................................................................................................................................................................
Toggle Bit2 Flag (dq)564................................................................................................................................................................
Programming/erasing Flash Memory565................................................................................................................................................................
Placing Flash Memory In Read/reset State566................................................................................................................................................................
Programming Data To Flash Memory567................................................................................................................................................................
Erasing All Data From Flash Memory (chip Erase)569................................................................................................................................................................
Erasing Specific Data From Flash Memory (sector Erase)570................................................................................................................................................................
Suspending Sector Erase From Flash Memory572................................................................................................................................................................
Resuming Sector Erase Of Flash Memory573................................................................................................................................................................
Unlock Bypass Program574................................................................................................................................................................
Flash Security577................................................................................................................................................................
Flash Memory Status Register 2 (fsr2)579................................................................................................................................................................
Flash Memory Status Register 2 (fsr)579................................................................................................................................................................
Flash Memory Status Register (fsr)582................................................................................................................................................................
Flash Memory Sector Write Control Register 0 (swre0)585................................................................................................................................................................
Flash Memory Status Register 3 (fsr3)587................................................................................................................................................................
Flash Memory Status Register 3 (fsr)587................................................................................................................................................................
Flash Memory Status Register 4 (fsr4)588................................................................................................................................................................
Flash Memory Status Register 4 (fsr)588................................................................................................................................................................
Notes On Using Dual Operation Flash Memory596................................................................................................................................................................
Chapter 26 Non-volatile Register (nvr) Interface597................................................................................................................................................................
Main Cr Clock Trimming Register (upper) (crth)601................................................................................................................................................................
Main Cr Clock Trimming Register (lower) (crtl)602................................................................................................................................................................
Main Cr Clock Temperature Dependent Adjustment Register (crtda)603................................................................................................................................................................
Watchdog Timer Selection Id Register (upper/lower) (wdth/wdtl)604................................................................................................................................................................
Notes On Main Cr Clock Trimming605................................................................................................................................................................
Notes On Using Nvr Interface607................................................................................................................................................................
Chapter 27 Comparator609................................................................................................................................................................
Comparator Control Register (cmr0c)617................................................................................................................................................................
Chapter 28 System Configuration Controller619................................................................................................................................................................
System Configuration Register (sysc)622................................................................................................................................................................
Notes On Using Controller624................................................................................................................................................................
Appendix625................................................................................................................................................................
Appendix A Instruction Overview626................................................................................................................................................................
A.1 Addressing629................................................................................................................................................................
A.2 Special Instruction633................................................................................................................................................................
Special Instruction633................................................................................................................................................................
A.3 Bit Manipulation Instructions (setb, Clrb)637................................................................................................................................................................
Instruction Map641................................................................................................................................................................

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