Oscillation Stabilization Wait Time And Pll Lock Wait Time - Fujitsu FR60 Hardware Manual

3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait
Time
If a clock selected as the source clock is not already stabilized, an oscillation
stabilization wait time is required (See Section "3.11.4 Oscillation Stabilization Wait
Time").
For a PLL, a lock wait time is required after operation starts until the output stabilizes
to the specified frequency.
This section describes the wait time used in various situations.
❍ Wait time after power-on
After power-on, an oscillation stabilization wait time for the main clock oscillation circuit is
required.
Since the oscillation stabilization wait time setting is initialized to the minimum value due to INIT
pin input (settings initialization reset pin), assure the oscillation stabilization wait time by using
the time during which the "L" level is sent to the INIT pin input.
In this state, since no PLL is enabled, no lock wait time needs to be considered.
❍ Wait time after setting initialization
If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait
state. In this case, the specified oscillation stabilization wait is internally generated. In the first
oscillation stabilization wait state after input from the INIT pin, the setting time is initialized to the
minimum value, soon ending this state, and the device enters the operation initialization reset
(RST) state.
If, after a program starts running, a settings initialization reset (INIT) is generated for a reason
other than INIT pin input and is then cleared, the oscillation stabilization wait time specified in
the program is internally generated.
In these states, since no PLL is enabled, no lock wait time needs to be considered.
❍ Wait time after changing the PLL multiply-by rate
If you change the multiply-by rate setting of a running PLL after a program starts execution, use
the PLL output only after lock wait time elapses.
If the PLL is not selected as the source clock, the program can run even during the lock wait
time.
For the PLL lock wait time, use of a time-base timer interrupt is recommended.
❍ Wait time after returning from stop mode
If, after a program starts execution, the device enters stop mode and then stop mode is cleared,
the oscillation stabilization wait time specified in the program is internally generated. If the clock
oscillation circuit selected as the source clock is set to stop in stop mode, the oscillation
stabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whichever
is longer, is required. Set the oscillation stabilization wait time before entering stop mode.
If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the
PLL does not automatically stop. No oscillation stabilization wait time is required unless the PLL
has stopped. Setting the oscillation stabilization wait time to the minimum value before stop
mode is entered is recommended.
CHAPTER 3 CPU AND CONTROL UNITS
105