Status Register System - Keysight x-series User Reference Manual

When a register set causes a summary bit in the status byte to change from 0 to 1, the instrument can
initiate the service request (SRQ) process. However, the process is only initiated if both of the following
conditions are true:
• The corresponding bit of the service request enable register is also set to 1.
• The instrument does not have a service request pending. (A service request is considered to be pending
between the time the instrument's SRQ process is initiated and the time the controller reads the status
byte register.)
The SRQ process sets the SRQ true. It also sets the status byte's request service (RQS) bit to 1. Both
actions are necessary to inform the controller that the instrument requires service. Setting the SRQ line
only informs the controller that some device on the bus requires service. Setting the RQS bit allows the
controller to determine which instrument requires service.
If your program enables the controller to detect and respond to service requests, it should instruct the
controller to perform a serial poll when the SRQ is set true. Each device on the bus returns the contents of
its status byte register in response to this poll. The device who's RQS bit is set to 1 is the device that
requested service.
When you read the instrument's status byte register with a serial poll, the RQS bit is reset to 0. Other bits in
the register are not affected.
If the status register is configured to SRQ on end-of-measurement and the measurement is in continuous
mode, then restarting a measurement (INIT command) can cause the measuring bit to pulse low. This
causes an SRQ when you have not actually reached the "end-of-measurement" condition. To avoid this:
1. Set INITiate:CONTinuous off.
2. Set/enable the status registers.
3. Restart the measurement (send INIT).

Status Register System

The hardware status registers are combined to form the instrument status system. Specific status bits are
assigned to monitor various aspects of the instrument operation and status. See the diagram of the status
system above for information about the bit assignments and status register interconnections.
EMI Receiver Mode Reference
3 Programming the Analyzer
STATus Subsystem
105