Status Register System - Keysight N9320B Programmer's Manual

Status Registers

Status Register System

Status Register System
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Setting Limited/Readjusted
Always Zero
STATus:QUEStionable:INTegrity
28
The hardware status registers are combined to form the instrument
status system. Specific status bits are assigned to monitor various
aspects of the instrument operation and status. See the following
diagram of the status system for information about the bit
assignments and status register interconnections.
Figure 1
0
1
2
3
4
5
6
7
+
8
9
10
Oper. Complete
11
Req. Bus Control
12
Query Error
13
Dev. Dep. Error
14
Execution Error
15
Command Error
Reserved
Power on
Standard Event Status Register
(*ESE,*ESE?,*ESR?,*OPC)
Reserved
Reserved
Reserved
Reserved
MEASuring
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Always Zero
Standard OPERation
Keysight N9320B Status Register System
Status Byte Register (*STB?)
Unused
Unused
Error/Event Queue Summary
Questionable Status Summary
Message Available (MAV)
Std. Event Status Sum
Req. Serv. Sum (RQS)
Operation Status Sum
0
1
2
3
+
4
5
6
7
0
1
2
3
4
5
6
7
+
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
&
&
&
&
&
+
&
&
&
7 6 5 4 3 2 1 0
Service Request Enable Register
(*SRE,*SRE?)