Status Register System - Keysight N9322C Programmer's Manual

Status Register System

Setting and Querying the Status Register
The hardware status registers are combined to form the
instrument status system. Specific status bits are assigned to
monitor various aspects of the instrument operation and
status. See the following diagram of the status system for
information about the bit assignments and status register
interconnections.
Figure 1 Keysight N9322C Status Register System
Error/Event Queue Summary
Message Available (MAV)
Std. Event Status Sum
Unused
0
Unused 1
Query Error 2
Dev. Dep. Error
3
Unused
4
Command Error
5
Reserved 6
Power On
7
Standard Event Status Register
(*ESE,*ESE?,*ESR?,*)
Each bit in a register is represented by a numerical value
based on its location. This number is sent with the
command to enable a particular bit. To enable more than
one bit, send the sum of all of the bits involved.
For example, to enable bit 0 and bit 6 of the standard event
status register, you would send the command *ESE 65 (1 +
64).
Status Register System
Status Byte Register
Unused
0
Unused
1
2
3
Unused
4
5
Unused
6
Reserved 7
+
+
&
7 6 5 4 3 2 1 0
Service Request Enable Register
Status Registers
(*STB?)
&
&
&
&
&
&
(*SRE,*SRE?)
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