Motorola PowerQUICC II MPC8280 Series Reference Manual page 60

Figure
Number
28-4 SMC Function Code Registers (RFCR/TFCR)......................................................... 28-9
28-5 SMC UART Frame Format..................................................................................... 28-12
28-6 SMC UART RxBD ................................................................................................. 28-16
28-7 RxBD Example ....................................................................................................... 28-18
28-8 SMC UART TxBD.................................................................................................. 28-19
28-9 SMC UART Event Register (SMCE)/Mask Register (SMCM) ............................. 28-20
28-10 SMC UART Interrupts Example............................................................................. 28-21
28-11 Synchronization with SMSYNx.............................................................................. 28-25
28-12 Synchronization with the TSA ................................................................................ 28-26
28-13 SMC Transparent RxBD ......................................................................................... 28-28
28-14 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ..................... 28-31
28-15 SMC Monitor Channel RxBD................................................................................. 28-35
28-16 SMC Monitor Channel TxBD................................................................................. 28-36
28-17 SMC C/I Channel RxBD......................................................................................... 28-36
28-18 SMC C/I Channel TxBD......................................................................................... 28-37
28-19 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ................................. 28-37
29-1 BD Structure for One MCC ...................................................................................... 29-4
29-2 TSTATE High Byte ................................................................................................... 29-8
29-3 INTMSK Mask Bits .................................................................................................. 29-8
29-4 Channel Mode Register (CHAMR) .......................................................................... 29-9
29-5 Rx Internal State (RSTATE) High Byte .................................................................. 29-11
29-6 Channel Mode Register (CHAMR)—Transparent Mode ....................................... 29-13
29-7 INTMSK Mask Bits ................................................................................................ 29-16
29-8 Channel Mode Register (CHAMR)—CES Mode................................................... 29-16
29-9 Extended Channel Mode Register (ECHAMR)...................................................... 29-22
29-10 SS7 Configuration Register (SS7_OPT) ................................................................. 29-25
29-11 Mask1 Format ......................................................................................................... 29-27
29-12 Mask2 Format ......................................................................................................... 29-27
29-13 Super Channel Table Entry ..................................................................................... 29-31
29-14 Transmitter Super Channel Example ...................................................................... 29-32
29-15 Receiver Super Channel with Slot Synchronization Example................................ 29-33
29-16 Receiver Super Channel without Slot Synchronization Example........................... 29-34
29-17 SI MCC Configuration Register (MCCF)............................................................... 29-34
29-18 Interrupt Circular Table........................................................................................... 29-37
29-19 MCC Event Register (MCCE)/Mask Register (MCCM)........................................ 29-38
29-20 Interrupt Circular Table Entry................................................................................. 29-40
29-21 MCC Receive Buffer Descriptor (RxBD)............................................................... 29-45
29-22 MCC Transmit Buffer Descriptor (TxBD).............................................................. 29-47
30-1 FCC Block Diagram.................................................................................................. 30-3
30-2 General FCC Mode Register (GFMR)...................................................................... 30-4
30-3 General FCC Expansion Mode Register (GFEMR) ................................................. 30-7
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Freescale Semiconductor, Inc.
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MPC8280 PowerQUICC II Family Reference Manual
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