Motorola PowerQUICC II MPC8280 Series Reference Manual page 58

Figure
Number
20-14 DPLL Transmitter Block Diagram.......................................................................... 20-23
20-15 DPLL Encoding Examples...................................................................................... 20-25
21-1 UART Character Format ........................................................................................... 21-1
21-2 Two UART Multidrop Configurations...................................................................... 21-8
21-3 Control Character Table ............................................................................................ 21-9
21-4 Transmit Out-of-Sequence Register (TOSEQ) ....................................................... 21-10
21-5 Asynchronous UART Transmitter .......................................................................... 21-12
21-6 Protocol-Specific Mode Register for UART (PSMR) ............................................ 21-14
21-7 SCC UART Receiving Using RxBDs ..................................................................... 21-17
21-8 SCC UART Receive Buffer Descriptor (RxBD) .................................................... 21-18
21-9 SCC UART Transmit Buffer Descriptor (TxBD) ................................................... 21-19
21-10 SCC UART Interrupt Event Example ..................................................................... 21-21
21-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) ......................... 21-21
21-12 SCC Status Register for UART Mode (SCCS) ....................................................... 21-22
22-1 HDLC Framing Structure.......................................................................................... 22-2
22-2 HDLC Address Recognition ..................................................................................... 22-5
22-3 HDLC Mode Register (PSMR)................................................................................. 22-7
22-4 SCC HDLC Receive Buffer Descriptor (RxBD) ...................................................... 22-9
22-5 SCC HDLC Receiving Using RxBDs..................................................................... 22-11
22-6 SCC HDLC Transmit Buffer Descriptor (TxBD) ................................................... 22-12
22-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ............................ 22-13
22-8 SCC HDLC Interrupt Event Example..................................................................... 22-15
22-9 CC HDLC Status Register (SCCS) ......................................................................... 22-15
22-10 Typical HDLC Bus Multi-Master Configuration.................................................... 22-20
22-11 Typical HDLC Bus Single-Master Configuration................................................... 22-21
22-12 Detecting an HDLC Bus Collision.......................................................................... 22-22
22-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ....................... 22-23
22-14 HDLC Bus Transmission Line Configuration ........................................................ 22-23
22-15 Delayed RTS Mode ................................................................................................. 22-24
22-16 HDLC Bus TDM Transmission Line Configuration .............................................. 22-24
23-1 Classes of BISYNC Frames ...................................................................................... 23-1
23-2 Control Character Table and RCCM......................................................................... 23-6
23-3 BISYNC SYNC (BSYNC) ....................................................................................... 23-8
23-4 BISYNC DLE (BDLE) ............................................................................................. 23-8
23-5 Protocol-Specific Mode Register for BISYNC (PSMR) ........................................ 23-10
23-6 SCC BISYNC RxBD .............................................................................................. 23-12
23-7 SCC BISYNC Transmit BD (TxBD) ...................................................................... 23-14
23-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)..................... 23-16
23-9 SCC Status Registers (SCCS) ................................................................................. 23-16
24-1 Sending Transparent Frames Between MPC8280s................................................... 24-5
24-2 SCC Transparent Receive Buffer Descriptor (RxBD) .............................................. 24-9
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Freescale Semiconductor, Inc.
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MPC8280 PowerQUICC II Family Reference Manual
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