Motorola PowerQUICC II MPC8280 Series Reference Manual page 66

Figure
Number
39-4 SPMODE—SPI Mode Register ................................................................................ 39-7
39-5 SPI Transfer Format with SPMODE[CP] = 0........................................................... 39-8
39-6 SPI Transfer Format with SPMODE[CP] = 1........................................................... 39-9
39-7 SPIE/SPIM—SPI Event/Mask Registers ................................................................ 39-11
39-8 SPCOM—SPI Command Register ......................................................................... 39-11
39-9 RFCR/TFCR—Function Code Registers................................................................ 39-13
39-10 SPI Memory Structure............................................................................................. 39-15
39-11 SPI RxBD................................................................................................................ 39-16
39-12 SPI TxBD................................................................................................................ 39-17
2
40-1 I C Controller Block Diagram .................................................................................. 40-1
2
40-2 I C Master/Slave General Configuration.................................................................. 40-2
2
40-3 I C Transfer Timing .................................................................................................. 40-3
2
40-4 I C Master Write Timing .......................................................................................... 40-4
2
40-5 I C Master Read Timing ........................................................................................... 40-5
2
40-6 I C Mode Register (I2MOD) .................................................................................... 40-6
2
40-7 I C Address Register (I2ADD) ................................................................................. 40-7
2
40-8 I C Baud Rate Generator Register (I2BRG)............................................................. 40-8
2
40-9 I C Event/Mask Registers (I2CER/I2CMR)............................................................. 40-8
2
40-10 I C Command Register (I2COM) ............................................................................. 40-9
2
40-11 I C Function Code Registers (RFCR/TFCR).......................................................... 40-11
2
40-12 I C Memory Structure............................................................................................. 40-12
2
40-13 I C RxBD................................................................................................................ 40-13
2
40-14 I C TxBD ................................................................................................................ 40-14
41-1 Port Open-Drain Registers (PODRA–PODRD) ....................................................... 41-2
41-2 Port Data Registers (PDATA–PDATD) .................................................................... 41-3
41-3 Port Data Direction Register (PDIR) ........................................................................ 41-3
41-4 Port Pin Assignment Register (PPARA–PPARD)..................................................... 41-4
41-5 Special Options Registers (PSORA–POSRD).......................................................... 41-5
41-6 Port Functional Operation ......................................................................................... 41-6
41-7 Primary and Secondary Option Programming .......................................................... 41-8
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Freescale Semiconductor, Inc.
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Title
MPC8280 PowerQUICC II Family Reference Manual
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