Motorola PowerQUICC II MPC8280 Series Reference Manual page 52

Figure
Number
9-32 PCI Bridge PCI Configuration Registers .................................................................. 9-50
9-33 Vendor ID Register.................................................................................................... 9-51
9-34 Device ID Register.................................................................................................... 9-51
9-35 PCI Bus Command Register ..................................................................................... 9-52
9-36 PCI Bus Status Register ............................................................................................ 9-53
9-37 Revision ID Register ................................................................................................. 9-54
9-38 PCI Bus Programming Interface Register................................................................. 9-54
9-39 Subclass Code Register ............................................................................................. 9-55
9-40 PCI Bus Base Class Code Register ........................................................................... 9-55
9-41 PCI Bus Cache Line Size Register............................................................................ 9-56
9-42 PCI Bus Latency Timer Register .............................................................................. 9-56
9-43 Header Type Register................................................................................................ 9-57
9-44 BIST Control Register .............................................................................................. 9-57
9-45 PCI Bus Internal Memory-Mapped Registers Base Address Register
(PIMMRBAR)...................................................................................................... 9-58
9-46 General Purpose Local Access Base Address Registers (GPLABARx)................... 9-59
9-47 Subsystem Vendor ID Register ................................................................................. 9-59
9-48 Subsystem Device ID Register ................................................................................. 9-60
9-49 PCI Bus Capabilities Pointer Register ...................................................................... 9-60
9-50 PCI Bus Interrupt Line Register................................................................................ 9-61
9-51 PCI Bus Interrupt Pin Register.................................................................................. 9-61
9-52 PCI Bus MIN GNT ................................................................................................... 9-62
9-53 PCI Bus MAX LAT................................................................................................... 9-62
9-54 PCI Bus Function Register........................................................................................ 9-63
9-55 PCI Bus Arbiter Configuration Register ................................................................... 9-64
9-56 Hot Swap Register Block.......................................................................................... 9-65
9-57 Hot Swap Control Status Register............................................................................. 9-65
9-58 Data Structure for Register Initialization .................................................................. 9-69
9-59 PCI Configuration Data Structure for the EEPROM ................................................ 9-70
9-60 Inbound Message Registers (IMRx) ......................................................................... 9-71
9-61 Outbound Message Registers (OMRx) ..................................................................... 9-72
9-62 Outbound Doorbell Register (ODR) ......................................................................... 9-73
9-63 Inbound Doorbell Register (IDR) ............................................................................. 9-73
9-64 I O Message Queue .................................................................................................. 9-75
2
9-65 Inbound Free_FIFO Head Pointer Register (IFHPR) ............................................... 9-76
9-66 Inbound Free_FIFO Tail Pointer Register (IFTPR) .................................................. 9-77
9-67 Inbound Post_FIFO Head Pointer Register (IPHPR) ............................................... 9-78
9-68 Inbound Post_FIFO Tail Pointer Register (IPTPR) .................................................. 9-79
9-69 Outbound Free_FIFO Head Pointer Register (OFHPR) ........................................... 9-80
9-70 Outbound Free_FIFO Tail Pointer Register (OFTPR).............................................. 9-81
9-71 Outbound Post_FIFO Head Pointer Register (OPHPR) ........................................... 9-82
lii
Freescale Semiconductor, Inc.
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Title
MPC8280 PowerQUICC II Family Reference Manual
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