ST STM32F215VE Manuals
Manuals and User Guides for ST STM32F215VE. We have 1 ST STM32F215VE manual available for free PDF download: Reference Manual
ST STM32F215VE Reference Manual (1381 pages)
Advanced Arm-based 32-bit MCUs
Brand: ST
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Category: Microcontrollers
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Size: 18 MB
Table of Contents
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Glossary46
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S0: I-Bus49
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S1: D-Bus49
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S2: S-Bus49
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Busmatrix50
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Memory Map51
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Bit Banding54
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Sleep Mode73
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Stop Mode74
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Standby Mode76
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Reset84
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System Reset84
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Power Reset85
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Clocks86
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HSE Clock88
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HSI Clock89
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LSE Clock90
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LSI Clock91
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RCC Register Map135
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Port Pins148
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(X = a151
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GPIO Registers151
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(X = a152
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(X = a154
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(X = a156
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SYSCFG Registers159
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(Syscfg_Exticr1)160
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(Syscfg_Exticr2)161
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(Syscfg_Exticr3)161
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(Syscfg_Exticr4)162
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NVIC Features164
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EXTI Registers172
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DMA Introduction176
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DMA Transactions179
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Arbiter181
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DMA Streams181
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Circular Mode186
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Fifo190
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Flow Controller194
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Error Management196
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DMA Interrupts197
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DMA Registers198
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DMA Register Map208
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ADC Introduction212
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ADC Clock214
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Analog Watchdog216
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Timing Diagram216
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Scan Mode217
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Data Alignment220
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Data Management224
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Using the DMA224
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Multi ADC Mode225
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Interleaved Mode231
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ADC Interrupts238
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ADC Registers239
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(Adc_Cdr)253
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DAC Introduction256
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DAC Data Format258
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DAC Conversion259
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DMA Request261
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Noise Generation261
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DAC Registers268
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(Dac_Dhr12L1)272
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(Dac_Dhr12L2)273
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(Dac_Dhr12Ld)274
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DAC Register Map276
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DCMI Clocks278
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DCMI Pins278
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DMA Interface280
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Synchronization282
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Capture Modes285
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Crop Feature286
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Data Formats288
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Fifo288
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JPEG Format288
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RGB Format289
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Ycbcr Format289
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DCMI Interrupts290
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Time-Base Unit306
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Counter Modes308
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Clock Selection319
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PWM Input Mode326
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PWM Mode328
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One-Pulse Mode338
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Debug Mode347
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Time-Base Unit378
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Counter Modes379
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Clock Selection389
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PWM Input Mode395
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PWM Mode397
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One-Pulse Mode400
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Debug Mode413
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Time-Base Unit440
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Counter Modes442
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Clock Selection445
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PWM Mode452
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One-Pulse Mode453
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Debug Mode458
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Time-Base Unit485
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Counting Mode487
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Clock Source489
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Debug Mode490
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Debug Mode497
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IWDG Registers498
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Debug Mode504
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Table 71. Table504
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WWDG Registers505
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Data Type522
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CRYP Busy State526
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Context Swapping528
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CRYP Interrupts530
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CRYP Registers531
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RNG Introduction544
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Error Management545
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Operation545
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RNG Registers545
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RNG Register Map548
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Data Type552
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Message Padding555
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Hash Operation556
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HMAC Operation556
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Context Swapping557
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HASH Interrupt558
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HASH Registers559
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Introduction570
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Tamper Detection579
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Alarm Output581
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RTC Interrupts581
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RTC Registers583
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(Rtc_Tafcr)595
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RTC Register Map596
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Mode Selection599
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I2C Slave Mode601
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I2C Master Mode604
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Error Conditions609
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Smbus610
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DMA Requests613
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I 2 C Interrupts615
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I 2 C Debug Mode617
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I 2 C Registers617
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I2C Register Map629
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Transmitter635
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Receiver638
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Parity Control654
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Smartcard660
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USART Interrupts669
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USART Registers670
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SPI Introduction682
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SPI Features683
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I 2 S Features684
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CRC Calculation700
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Status Flags702
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Error Flags706
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SPI Interrupts707
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Figure 269. I711
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Clock Generator716
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Figure 283. I717
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I 2 S Slave Mode720
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Status Flags722
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Error Flags723
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I 2 S Interrupts723
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Table 101. I723
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DMA Features724
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Mode)730
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SPI Register Map734
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SDIO Adapter739
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Card Reset750
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Block Write752
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Block Read753
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SD I/O Mode765
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R1B770
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Response Formats770
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R4 (Fast I/O)771
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R4B772
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SDIO Interrupts774
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Aborting CMD61775
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CE-ATA Interrupt775
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HW Flow Control776
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SDIO Registers776
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SDIO Response 1780
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Tx Mailboxes794
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Normal Mode796
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Silent Mode797
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Test Mode797
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Loop Back Mode798
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Debug Mode799
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Message Storage807
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Bit Timing809
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Error Management809
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Bxcan Interrupts811
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CAN Registers813
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DMA Controller838
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DMA Features840
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PTP Features840
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Ethernet Pins841
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MAC Interrupts866
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MAC Filtering867
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DMA Arbiter883
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DMA Interrupts906
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General Features958
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OTG Pins960
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USB Peripheral963
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USB Host967
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SRP-Capable Host968
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USB Host States968
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Host Channels970
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Host Scheduler971
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Host Sofs972
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SOF Trigger972
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Peripheral Sofs973
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USB Data Fifos975
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Host Rx FIFO977
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Device Mode978
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Host Tx Fifos978
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Host Mode979
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CSR Memory Map983
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Host-Mode Registers1009
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(Otg_Fs_Pcgcctl)1042
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OTG_FS Register Map1043
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Core Initialization1052
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Host Initialization1053
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Operational Model1072
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OTG_HS Introduction1098
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OTG_HS Main Features1098
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General Features1099
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Host-Mode Features1100
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High-Speed OTG PHY1101
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OTG Pins1101
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HNP Dual Role Device1102
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ID Line Detection1102
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OTG Dual-Role Device1102
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SRP Dual-Role Device1103
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Peripheral States1104
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Peripheral Endpoints1105
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SRP-Capable Host1108
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USB Host States1109
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Host Channels1110
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Host Scheduler1112
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Host Sofs1113
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Peripheral Sofs1113
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SOF Trigger1113
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FIFO RAM Allocation1116
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Host Mode1116
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Peripheral Mode1116
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OTG_HS Interrupts1117
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CSR Memory Map1119
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Host-Mode Registers1147
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(Otg_Hs_Pcgcctl)1189
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OTG_HS Register Map1189
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Core Initialization1204
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Host Initialization1205
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DMA Mode1206
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Operational Model1234
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FSMC Main Features1261
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AHB Interface1262
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Block Diagram1262
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General Timing Rules1270
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