Uart - Texas Instruments MSPM0G350 Series Manual

MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
7.20.2 SPI Timing Diagram
CS
(inverted)
t
CS, LEAD
CS
1 / f
SPI
SCLK
(SPO = 0)
t
t
SCLK_H/L SCLK_H/L
SCLK
(SPO = 1)
POCI
t
HD,CO
t t
CS, ACC VALID,CO
PICO
Controller Mode, SPH = 0
CS
(inverted)
t
CS, LEAD
CS
1 / f
SPI
SCLK
(SPO = 0)
t t
SCLK_H/L SCLK_H/L
SCLK
(SPO = 1)
PICO
t
HD,PO
t t
CS, ACC VALID,PO
POCI
Peripheral Mode, SPH = 0

7.21 UART

over operating free-air temperature range (unless otherwise noted)
PARAMETERS
f UART input clock frequency
UART
f UART input clock frequency
UART
BITCLK clock frequency(equals
f
BITCLK
baud rate in MBaud)
BITCLK clock frequency(equals
f
BITCLK
baud rate in MBaud)
50 Submit Document Feedback
t
CS, LAG
t
SU,CI
t
HD,CI
Figure 7-6. SPI Timing Diagram - Controller Mode
t
SU,PI
t
HD,PI
Figure 7-7. SPI Timing Diagram - Peripheral Mode
TEST CONDITIONS
UART in Power Domain1
UART in Power Domain0
UART in Power Domain1
UART in Power Domain0
Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
CS
(inverted)
t
CS, LEAD
CS
1 / f
SCLK
(SPO = 0)
t
SCLK_H/L
SCLK
(SPO = 1)
t
CS, ACC
POCI
t
CS, DIS
PICO
CS
(inverted)
t
CS, LEAD
CS
1 / f
t
CS, LAG
SCLK
(SPO = 0)
t
SCLK_H/L
SCLK
(SPO = 1)
PICO
t
CS, DIS t
CS, ACC
POCI
SPI
t
SCLK_H/L
t
SU,CI
t
HD,CI
t
HD,CO
t
VALID,CO
Controller Mode, SPH = 1
SPI
t
SCLK_H/L
t
SU,PI
t
HD,PI
t
HD,PO
t
VALID,PO
Peripheral Mode, SPH = 1
MIN TYP MAX
80
40
10
5
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
t
CS, LAG
t
CS, DIS
t
CS, LAG
t
CS, DIS
UNIT
MHz
MHz
MHz
MHz