ST STM32G4 Series Reference Manual page 1952

FD controller area network (FDCAN)
Bits 5: 3 Reserved, must be kept at reset value.
Bits 2: 0 BIDX: Buffer Index
43.4.22 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S)
Address offset: 0x0090
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31: 26 Reserved, must be kept at reset value.
Bit 25 RF0L: Rx FIFO 0 Message Lost
Bit 24 F0F: Rx FIFO 0 Full
Bits 23: 18 Reserved, must be kept at reset value.
Bits 17: 16 F0PI: Rx FIFO 0 Put Index
Bits 15: 10 Reserved, must be kept at reset value.
Bits 9: 8 F0GI: Rx FIFO 0 Get Index
Bits 7: 4 Reserved, must be kept at reset value.
Bits 3: 0 F0FL: Rx FIFO 0 Fill Level
43.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A)
Address offset: 0x0094
Reset value: 0x0000 0000
1952/2083
Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1.
28 27 26 25
Res. Res. RF0L
r
12 11 10 9
Res. Res. F0GI[1:0]
r
This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset.
0: No Rx FIFO 0 message lost
1: Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0
0: Rx FIFO 0 not full
1: Rx FIFO 0 full
Rx FIFO 0 write index pointer, range 0 to 2.
Rx FIFO 0 read index pointer, range 0 to 2.
Number of elements stored in Rx FIFO 0, range 0 to 3.
24 23 22
F0F Res. Res.
r
8 7 6
Res. Res.
r
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. F0FL[3:0]
r r
RM0440
17 16
F0PI[1:0]
r r
1 0
r r