ST STM32G4 Series Reference Manual page 1949

Advanced arm-based 32-bit mcus

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Address offset: 0x005C

Reset value: 0x0000 0000

Bits 31: 2 Reserved, must be kept at reset value.

Bit 1 EINT1: Enable Interrupt Line 1

Bit 0 EINT0: Enable Interrupt Line 0

FDCAN global filter configuration register (FDCAN_RXGFC)

Global settings for Message ID filtering. The Global Filter Configuration controls the filter

path for standard and extended messages as described in

Address offset: 0x0080

Reset value: 0x0000 0000

Bits 31: 28 Reserved, must be kept at reset value.

Bits 27: 24 LSE: List Size Extended

Bits 23: 21 Reserved, must be kept at reset value.

Bits 20: 16 LSS[4:0]: List Size Standard

0: Interrupt line fdcan_intr0_it disabled

1: Interrupt line fdcan_intr0_it enabled

0: Interrupt line fdcan_intr1_it disabled

1: Interrupt line fdcan_intr1_it enabled

0: No extended Message ID filter

1 to 8: Number of extended Message ID filter elements

>8: Values greater than 8 are interpreted as 8.

These are protected write (P) bits, which means that write access by the bits is possible

only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

0: No standard Message ID filter

1 to 28: Number of standard Message ID filter elements

>28: Values greater than 28 are interpreted as 28.

These are protected write (P) bits, which means that write access by the bits is possible

only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

FD controller area network (FDCAN)

RM0440 Rev 1

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